1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Sandy Huang <hjc@rock-chips.com>
6 */
7
8 #include <linux/module.h>
9 #include <linux/clk.h>
10 #include <linux/platform_device.h>
11 #include <linux/of.h>
12 #include <linux/regmap.h>
13 #include <linux/reset.h>
14 #include <linux/mfd/rk628.h>
15
16 #include <drm/drm_of.h>
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_panel.h>
21 #include <video/of_display_timing.h>
22 #include <video/videomode.h>
23
24 #include "rk628_combtxphy.h"
25
26 #define HOSTREG(x) ((x) + 0x80000)
27 #define GVI_SYS_CTRL0 HOSTREG(0x0000)
28 #define GVI_SYS_CTRL1 HOSTREG(0x0004)
29 #define GVI_SYS_CTRL2 HOSTREG(0x0008)
30 #define GVI_SYS_CTRL3 HOSTREG(0x000c)
31 #define GVI_VERSION HOSTREG(0x0010)
32 #define GVI_SYS_RST HOSTREG(0x0014)
33 #define GVI_LINE_FLAG HOSTREG(0x0018)
34 #define GVI_STATUS HOSTREG(0x001c)
35 #define GVI_PLL_LOCK_TIMEOUT HOSTREG(0x0030)
36 #define GVI_HTPDN_TIMEOUT HOSTREG(0x0034)
37 #define GVI_LOCKN_TIMEOUT HOSTREG(0x0038)
38 #define GVI_WAIT_LOCKN HOSTREG(0x003C)
39 #define GVI_WAIT_HTPDN HOSTREG(0x0040)
40 #define GVI_INTR_EN HOSTREG(0x0050)
41 #define GVI_INTR_CLR HOSTREG(0x0054)
42 #define GVI_INTR_RAW_STATUS HOSTREG(0x0058)
43 #define GVI_INTR_STATUS HOSTREG(0x005c)
44 #define GVI_COLOR_BAR_CTRL HOSTREG(0x0060)
45 #define GVI_COLOR_BAR_HTIMING0 HOSTREG(0x0070)
46 #define GVI_COLOR_BAR_HTIMING1 HOSTREG(0x0074)
47 #define GVI_COLOR_BAR_VTIMING0 HOSTREG(0x0078)
48 #define GVI_COLOR_BAR_VTIMING1 HOSTREG(0x007c)
49
50 /* SYS_CTRL0 */
51 #define SYS_CTRL0_GVI_EN BIT(0)
52 #define SYS_CTRL0_AUTO_GATING BIT(1)
53 #define SYS_CTRL0_FRM_RST_EN BIT(2)
54 #define SYS_CTRL0_FRM_RST_MODE BIT(3)
55 #define SYS_CTRL0_LANE_NUM_MASK GENMASK(7, 4)
56 #define SYS_CTRL0_LANE_NUM(x) UPDATE(x, 7, 4)
57 #define SYS_CTRL0_BYTE_MODE_MASK GENMASK(9, 8)
58 #define SYS_CTRL0_BYTE_MODE(x) UPDATE(x, 9, 8)
59 #define SYS_CTRL0_SECTION_NUM_MASK GENMASK(11, 10)
60 #define SYS_CTRL0_SECTION_NUM(x) UPDATE(x, 11, 10)
61 #define SYS_CTRL0_CDR_ENDIAN_SWAP BIT(12)
62 #define SYS_CTRL0_PACK_BYTE_SWAP BIT(13)
63 #define SYS_CTRL0_PACK_ENDIAN_SWAP BIT(14)
64 #define SYS_CTRL0_ENC8B10B_ENDIAN_SWAP BIT(15)
65 #define SYS_CTRL0_CDR_EN BIT(16)
66 #define SYS_CTRL0_ALN_EN BIT(17)
67 #define SYS_CTRL0_NOR_EN BIT(18)
68 #define SYS_CTRL0_ALN_NOR_MODE BIT(19)
69 #define SYS_CTRL0_GVI_MASK GENMASK(19, 16)
70 #define SYS_CTRL0_GVI_GN_EN(x) UPDATE(x, 19, 16)
71
72 #define SYS_CTRL0_SCRAMBLER_EN BIT(20)
73 #define SYS_CTRL0_ENCODE8B10B_EN BIT(21)
74 #define SYS_CTRL0_INIT_RD_EN BIT(22)
75 #define SYS_CTRL0_INIT_RD_VALUE BIT(23)
76 #define SYS_CTRL0_FORCE_HTPDN_EN BIT(24)
77 #define SYS_CTRL0_FORCE_HTPDN_VALUE BIT(25)
78 #define SYS_CTRL0_FORCE_PLL_EN BIT(26)
79 #define SYS_CTRL0_FORCE_PLL_VALUE BIT(27)
80 #define SYS_CTRL0_FORCE_LOCKN_EN BIT(28)
81 #define SYS_CTRL0_FORCE_LOCKN_VALUE BIT(29)
82
83 /* SYS_CTRL1 */
84 #define SYS_CTRL1_COLOR_DEPTH_MASK GENMASK(3, 0)
85 #define SYS_CTRL1_COLOR_DEPTH(x) UPDATE(x, 3, 0)
86 #define SYS_CTRL1_DUAL_PIXEL_EN BIT(4)
87 #define SYS_CTRL1_TIMING_ALIGN_EN BIT(8)
88 #define SYS_CTRL1_LANE_ALIGN_EN BIT(9)
89
90 #define SYS_CTRL1_DUAL_PIXEL_SWAP BIT(12)
91 #define SYS_CTRL1_RB_SWAP BIT(13)
92 #define SYS_CTRL1_YC_SWAP BIT(14)
93 #define SYS_CTRL1_WHOLE_FRM_EN BIT(16)
94 #define SYS_CTRL1_NOR_PROTECT BIT(17)
95 #define SYS_CTRL1_RD_WCNT_UPDATE BIT(31)
96
97 /* SYS_CTRL2 */
98 #define SYS_CTRL2_AFIFO_READ_THOLD_MASK GENMASK(7, 0)
99 #define SYS_CTRL2_AFIFO_READ_THOLD(x) UPDATE(x, 7, 0)
100 #define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD_MASK GENMASK(23, 16)
101 #define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD(x) UPDATE(x, 23, 16)
102 #define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD_MASK GENMASK(31, 24)
103 #define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD(x) UPDATE(x, 31, 24)
104
105 /* SYS_CTRL3 */
106 #define SYS_CTRL3_LANE0_SEL_MASK GENMASK(2, 0)
107 #define SYS_CTRL3_LANE0_SEL(x) UPDATE(x, 2, 0)
108 #define SYS_CTRL3_LANE1_SEL_MASK GENMASK(6, 4)
109 #define SYS_CTRL3_LANE1_SEL(x) UPDATE(x, 6, 4)
110 #define SYS_CTRL3_LANE2_SEL_MASK GENMASK(10, 8)
111 #define SYS_CTRL3_LANE2_SEL(x) UPDATE(x, 10, 8)
112 #define SYS_CTRL3_LANE3_SEL_MASK GENMASK(14, 12)
113 #define SYS_CTRL3_LANE3_SEL(x) UPDATE(x, 14, 12)
114 #define SYS_CTRL3_LANE4_SEL_MASK GENMASK(18, 16)
115 #define SYS_CTRL3_LANE4_SEL(x) UPDATE(x, 18, 16)
116 #define SYS_CTRL3_LANE5_SEL_MASK GENMASK(22, 20)
117 #define SYS_CTRL3_LANE5_SEL(x) UPDATE(x, 22, 20)
118 #define SYS_CTRL3_LANE6_SEL_MASK GENMASK(26, 24)
119 #define SYS_CTRL3_LANE6_SEL(x) UPDATE(x, 26, 24)
120 #define SYS_CTRL3_LANE7_SEL_MASK GENMASK(30, 28)
121 #define SYS_CTRL3_LANE7_SEL(x) UPDATE(x, 30, 28)
122 /* VERSIION */
123 #define VERSION_VERSION(x) UPDATE(x, 31, 0)
124 /* SYS_RESET*/
125 #define SYS_RST_SOFT_RST BIT(0)
126 /* LINE_FLAG */
127 #define LINE_FLAG_LANE_FLAG0_MASK GENMASK(15, 0)
128 #define LINE_FLAG_LANE_FLAG0(x) UPDATE(x, 15, 0)
129 #define LINE_FLAG_LANE_FLAG1_MASK GENMASK(31, 16)
130 #define LINE_FLAG_LANE_FLAG1(x) UPDATE(x, 31, 16)
131 /* STATUS */
132 #define STATUS_HTDPN BIT(4)
133 #define STATUS_LOCKN BIT(5)
134 #define STATUS_PLL_LOCKN BIT(6)
135 #define STATUS_AFIFO0_WCNT_MASK GENMASK(23, 16)
136 #define STATUS_AFIFO0_WCNT(x) UPDATE(x, 23, 16)
137 #define STATUS_AFIFO1_WCNT_MASK GENMASK(31, 24)
138 #define STATUS_AFIFO1_WCNT(x) UPDATE(x, 31, 24)
139 /* PLL_LTIMEOUT */
140 #define PLL_LOCK_TIMEOUT_PLL_LOCK_TIME_OUT_MASK GENMASK(31, 0)
141 #define PLL_LOCK_TIMEOUT_PLL_LOCK_TIME_OUT(x) UPDATE(x, 31, 0)
142 /* HTPDNEOUT */
143 #define HTPDN_TIMEOUT_HTPDN_TIME_OUT_MASK GENMASK(31, 0)
144 #define HTPDN_TIMEOUT_HTPDN_TIME_OUT(x) UPDATE(x, 31, 0)
145 /* LOCKNEOUT */
146 #define LOCKN_TIMEOUT_LOCKN_TIME_OUT_MASK GENMASK(31, 0)
147 #define LOCKN_TIMEOUT_LOCKN_TIME_OUT(x) UPDATE(x, 31, 0)
148 /* WAIT_LOCKN */
149 #define WAIT_LOCKN_WAIT_LOCKN_TIME_MASK GENMASK(30, 0)
150 #define WAIT_LOCKN_WAIT_LOCKN_TIME(x) UPDATE(x, 30, 0)
151 #define WAIT_LOCKN_WAIT_LOCKN_TIME_EN BIT(31)
152 /* WAIT_HTPDN */
153 #define WAIT_HTPDN_WAIT_HTPDN_TIME_MASK GENMASK(30, 0)
154 #define WAIT_HTPDN_WAIT_HTPDN_TIME(x) UPDATE(x, 30, 0)
155 #define WAIT_HTPDN_WAIT_HTPDN_EN BIT(31)
156 /* INTR_EN */
157 #define INTR_EN_INTR_FRM_ST_EN BIT(0)
158 #define INTR_EN_INTR_PLL_LOCK_EN BIT(1)
159 #define INTR_EN_INTR_HTPDN_EN BIT(2)
160 #define INTR_EN_INTR_LOCKN_EN BIT(3)
161 #define INTR_EN_INTR_PLL_TIMEOUT_EN BIT(4)
162 #define INTR_EN_INTR_HTPDN_TIMEOUT_EN BIT(5)
163 #define INTR_EN_INTR_LOCKN_TIMEOUT_EN BIT(6)
164 #define INTR_EN_INTR_LINE_FLAG0_EN BIT(8)
165 #define INTR_EN_INTR_LINE_FLAG1_EN BIT(9)
166 #define INTR_EN_INTR_AFIFO_OVERFLOW_EN BIT(10)
167 #define INTR_EN_INTR_AFIFO_UNDERFLOW_EN BIT(11)
168 #define INTR_EN_INTR_PLL_ERR_EN BIT(12)
169 #define INTR_EN_INTR_HTPDN_ERR_EN BIT(13)
170 #define INTR_EN_INTR_LOCKN_ERR_EN BIT(14)
171 /* INTR_CLR*/
172 #define INTR_CLR_INTR_FRM_ST_CLR BIT(0)
173 #define INTR_CLR_INTR_PLL_LOCK_CLR BIT(1)
174 #define INTR_CLR_INTR_HTPDN_CLR BIT(2)
175 #define INTR_CLR_INTR_LOCKN_CLR BIT(3)
176 #define INTR_CLR_INTR_PLL_TIMEOUT_CLR BIT(4)
177 #define INTR_CLR_INTR_HTPDN_TIMEOUT_CLR BIT(5)
178 #define INTR_CLR_INTR_LOCKN_TIMEOUT_CLR BIT(6)
179 #define INTR_CLR_INTR_LINE_FLAG0_CLR BIT(8)
180 #define INTR_CLR_INTR_LINE_FLAG1_CLR BIT(9)
181 #define INTR_CLR_INTR_AFIFO_OVERFLOW_CLR BIT(10)
182 #define INTR_CLR_INTR_AFIFO_UNDERFLOW_CLR BIT(11)
183 #define INTR_CLR_INTR_PLL_ERR_CLR BIT(12)
184 #define INTR_CLR_INTR_HTPDN_ERR_CLR BIT(13)
185 #define INTR_CLR_INTR_LOCKN_ERR_CLR BIT(14)
186 /* INTR_RAW_STATUS */
187 #define INTR_RAW_STATUS_RAW_INTR_FRM_ST BIT(0)
188 #define INTR_RAW_STATUS_RAW_INTR_PLL_LOCK BIT(1)
189 #define INTR_RAW_STATUS_RAW_INTR_HTPDN BIT(2)
190 #define INTR_RAW_STATUS_RAW_INTR_LOCKN BIT(3)
191 #define INTR_RAW_STATUS_RAW_INTR_PLL_TIMEOUT BIT(4)
192 #define INTR_RAW_STATUS_RAW_INTR_HTPDN_TIMEOUT BIT(5)
193 #define INTR_RAW_STATUS_RAW_INTR_LOCKN_TIMEOUT BIT(6)
194 #define INTR_RAW_STATUS_RAW_INTR_LINE_FLAG0 BIT(8)
195 #define INTR_RAW_STATUS_RAW_INTR_LINE_FLAG1 BIT(9)
196 #define INTR_RAW_STATUS_RAW_INTR_AFIFO_OVERFLOW BIT(10)
197 #define INTR_RAW_STATUS_RAW_INTR_AFIFO_UNDERFLOW BIT(11)
198 #define INTR_RAW_STATUS_RAW_INTR_PLL_ERR BIT(12)
199 #define INTR_RAW_STATUS_RAW_INTR_HTPDN_ERR BIT(13)
200 #define INTR_RAW_STATUS_RAW_INTR_LOCKN_ERR BIT(14)
201 /* INTR_STATUS */
202 #define INTR_STATUS_INTR_FRM_ST BIT(0)
203 #define INTR_STATUS_INTR_PLL_LOCK BIT(1)
204 #define INTR_STATUS_INTR_HTPDN BIT(2)
205 #define INTR_STATUS_INTR_LOCKN BIT(3)
206 #define INTR_STATUS_INTR_PLL_TIMEOUT BIT(4)
207 #define INTR_STATUS_INTR_HTPDN_TIMEOUT BIT(5)
208 #define INTR_STATUS_INTR_LOCKN_TIMEOUT BIT(6)
209 #define INTR_STATUS_INTR_LINE_FLAG0 BIT(8)
210 #define INTR_STATUS_INTR_LINE_FLAG1 BIT(9)
211 #define INTR_STATUS_INTR_AFIFO_OVERFLOW BIT(10)
212 #define INTR_STATUS_INTR_AFIFO_UNDERFLOW BIT(11)
213 #define INTR_STATUS_INTR_PLL_ERR BIT(12)
214 #define INTR_STATUS_INTR_HTPDN_ERR BIT(13)
215 #define INTR_STATUS_INTR_LOCKN_ERR BIT(14)
216
217 /* COLOR_BAR_CTRL */
218 #define COLOR_BAR_EN BIT(0)
219
220 #define COLOR_DEPTH_RGB_YUV444_18BIT 0
221 #define COLOR_DEPTH_RGB_YUV444_24BIT 1
222 #define COLOR_DEPTH_RGB_YUV444_30BIT 2
223 #define COLOR_DEPTH_YUV422_16BIT 8
224 #define COLOR_DEPTH_YUV422_20BIT 9
225
226 enum gvi_byte_mode {
227 GVI_3BYTE_MODE = 0,
228 GVI_4BYTE_MODE,
229 GVI_5BYTE_MODE,
230 };
231
232 struct rk628_gvi {
233 struct drm_bridge base;
234 struct drm_connector connector;
235 struct drm_panel *panel;
236 struct drm_display_mode mode;
237 struct device *dev;
238 struct regmap *grf;
239 struct regmap *regmap;
240 struct clk *pclk;
241 struct reset_control *rst;
242 struct phy *phy;
243 struct rk628 *parent;
244 u32 lane_mbps;
245 u32 bus_format;
246 u32 lane_num;
247 u8 color_depth;
248 u8 byte_mode;
249 bool division_mode;
250 };
251
bridge_to_gvi(struct drm_bridge * b)252 static inline struct rk628_gvi *bridge_to_gvi(struct drm_bridge *b)
253 {
254 return container_of(b, struct rk628_gvi, base);
255 }
256
connector_to_gvi(struct drm_connector * c)257 static inline struct rk628_gvi *connector_to_gvi(struct drm_connector *c)
258 {
259 return container_of(c, struct rk628_gvi, connector);
260 }
261
rk628_gvi_connector_best_encoder(struct drm_connector * connector)262 static struct drm_encoder *rk628_gvi_connector_best_encoder(struct drm_connector
263 *connector)
264 {
265 struct rk628_gvi *gvi = connector_to_gvi(connector);
266
267 return gvi->base.encoder;
268 }
269
rk628_gvi_connector_get_modes(struct drm_connector * connector)270 static int rk628_gvi_connector_get_modes(struct drm_connector *connector)
271 {
272 struct rk628_gvi *gvi = connector_to_gvi(connector);
273 struct drm_display_info *info = &connector->display_info;
274 int num_modes;
275
276 num_modes = drm_panel_get_modes(gvi->panel, connector);
277
278 if (info->num_bus_formats)
279 gvi->bus_format = info->bus_formats[0];
280 else
281 gvi->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
282
283 switch (gvi->bus_format) {
284 case MEDIA_BUS_FMT_RGB666_1X18:
285 gvi->byte_mode = 3;
286 gvi->color_depth = COLOR_DEPTH_RGB_YUV444_18BIT;
287 break;
288 case MEDIA_BUS_FMT_RGB888_1X24:
289 gvi->byte_mode = 4;
290 gvi->color_depth = COLOR_DEPTH_RGB_YUV444_24BIT;
291 break;
292 case MEDIA_BUS_FMT_RGB101010_1X30:
293 gvi->byte_mode = 4;
294 gvi->color_depth = COLOR_DEPTH_RGB_YUV444_30BIT;
295 break;
296 case MEDIA_BUS_FMT_YUYV8_1X16:
297 gvi->byte_mode = 3;
298 gvi->color_depth = COLOR_DEPTH_YUV422_16BIT;
299 break;
300 case MEDIA_BUS_FMT_YUYV10_1X20:
301 gvi->byte_mode = 3;
302 gvi->color_depth = COLOR_DEPTH_YUV422_20BIT;
303 break;
304 default:
305 gvi->byte_mode = 3;
306 gvi->color_depth = COLOR_DEPTH_RGB_YUV444_24BIT;
307 dev_info(gvi->dev, "unsupported bus_format: 0x%x\n",
308 gvi->bus_format);
309 break;
310 }
311
312 info->edid_hdmi_dc_modes = 0;
313 info->hdmi.y420_dc_modes = 0;
314 info->color_formats = 0;
315 info->max_tmds_clock = 300000;
316 connector->ycbcr_420_allowed = true;
317
318 num_modes += rk628_scaler_add_src_mode(gvi->parent, connector);
319
320 return num_modes;
321 }
322
323 static const
324 struct drm_connector_helper_funcs rk628_gvi_connector_helper_funcs = {
325 .get_modes = rk628_gvi_connector_get_modes,
326 .best_encoder = rk628_gvi_connector_best_encoder,
327 };
328
329 static enum drm_connector_status
rk628_gvi_connector_detect(struct drm_connector * connector,bool force)330 rk628_gvi_connector_detect(struct drm_connector *connector, bool force)
331 {
332 return connector_status_connected;
333 }
334
rk628_gvi_connector_destroy(struct drm_connector * connector)335 static void rk628_gvi_connector_destroy(struct drm_connector *connector)
336 {
337 drm_connector_cleanup(connector);
338 }
339
340 static const struct drm_connector_funcs rk628_gvi_connector_funcs = {
341 .detect = rk628_gvi_connector_detect,
342 .fill_modes = drm_helper_probe_single_connector_modes,
343 .destroy = rk628_gvi_connector_destroy,
344 .reset = drm_atomic_helper_connector_reset,
345 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
346 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
347 };
348
rk628_gvi_get_lane_rate(struct rk628_gvi * gvi)349 static unsigned int rk628_gvi_get_lane_rate(struct rk628_gvi *gvi)
350 {
351 struct device *dev = gvi->dev;
352 const struct drm_display_mode *mode = &gvi->mode;
353 u32 lane_bit_rate, min_lane_rate = 500000, max_lane_rate = 4000000;
354 u64 total_bw;
355
356 /* optional override of the desired bandwidth */
357 if (!of_property_read_u32
358 (dev->of_node, "rockchip,lane-rate", &lane_bit_rate))
359 return lane_bit_rate;
360
361 /**
362 * [ENCODER TOTAL BIT-RATE](bps) = [byte mode](byte) x 10 / [pixel clock](HZ)
363 *
364 * lane_bit_rate = [total bit-rate](bps) / [lane number]
365 *
366 * 500Mbps <= lane_bit_rate <= 4Gbps
367 */
368 total_bw = (unsigned long long)gvi->byte_mode * 10 * mode->clock; /* Kbps */
369 do_div(total_bw, gvi->lane_num);
370 lane_bit_rate = total_bw;
371
372 if (lane_bit_rate < min_lane_rate)
373 lane_bit_rate = min_lane_rate;
374 if (lane_bit_rate > max_lane_rate)
375 lane_bit_rate = max_lane_rate;
376
377 return lane_bit_rate;
378 }
379
rk628_gvi_enable_color_bar(struct rk628_gvi * gvi)380 static void rk628_gvi_enable_color_bar(struct rk628_gvi *gvi)
381 {
382 const struct drm_display_mode *mode = &gvi->mode;
383 struct videomode vm;
384 u16 hsync_len, hact_st, hact_end, htotal;
385 u16 vsync_len, vact_st, vact_end, vtotal;
386
387 drm_display_mode_to_videomode(mode, &vm);
388
389 if (gvi->division_mode) {
390 hsync_len = vm.hsync_len / 2;
391 hact_st = (vm.hsync_len + vm.hback_porch) / 2;
392 hact_end = (vm.hsync_len + vm.hback_porch + vm.hactive) / 2;
393 htotal = mode->htotal / 2;
394 } else {
395 hsync_len = vm.hsync_len;
396 hact_st = vm.hsync_len + vm.hback_porch;
397 hact_end = vm.hsync_len + vm.hback_porch + vm.hactive;
398 htotal = mode->htotal;
399 }
400 vsync_len = vm.vsync_len;
401 vact_st = vsync_len + vm.vback_porch;
402 vact_end = vact_st + vm.vactive;
403 vtotal = mode->vtotal;
404
405 regmap_write(gvi->regmap, GVI_COLOR_BAR_HTIMING0,
406 hact_st << 16 | hsync_len);
407 regmap_write(gvi->regmap, GVI_COLOR_BAR_HTIMING1,
408 (htotal - 1) << 16 | hact_end);
409 regmap_write(gvi->regmap, GVI_COLOR_BAR_VTIMING0,
410 vact_st << 16 | vsync_len);
411 regmap_write(gvi->regmap, GVI_COLOR_BAR_VTIMING1,
412 (vtotal - 1) << 16 | vact_end);
413 regmap_write_bits(gvi->regmap, GVI_COLOR_BAR_CTRL, COLOR_BAR_EN, 0);
414 }
415
rk628_gvi_pre_enable(struct rk628_gvi * gvi)416 static void rk628_gvi_pre_enable(struct rk628_gvi *gvi)
417 {
418 clk_prepare_enable(gvi->pclk);
419
420 /* gvi reset */
421 regmap_write_bits(gvi->regmap, GVI_SYS_RST, SYS_RST_SOFT_RST,
422 SYS_RST_SOFT_RST);
423 udelay(10);
424 regmap_write_bits(gvi->regmap, GVI_SYS_RST, SYS_RST_SOFT_RST, 0);
425 udelay(10);
426
427 regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, SYS_CTRL0_LANE_NUM_MASK,
428 SYS_CTRL0_LANE_NUM(gvi->lane_num - 1));
429 regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, SYS_CTRL0_BYTE_MODE_MASK,
430 SYS_CTRL0_BYTE_MODE(gvi->byte_mode ==
431 3 ? 0 : (gvi->byte_mode ==
432 4 ? 1 : 2)));
433 regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0,
434 SYS_CTRL0_SECTION_NUM_MASK,
435 SYS_CTRL0_SECTION_NUM(gvi->division_mode));
436 regmap_update_bits(gvi->grf, GRF_POST_PROC_CON, SW_SPLIT_EN,
437 gvi->division_mode ? SW_SPLIT_EN : 0);
438 regmap_write_bits(gvi->regmap, GVI_SYS_CTRL1, SYS_CTRL1_DUAL_PIXEL_EN,
439 gvi->division_mode ? SYS_CTRL1_DUAL_PIXEL_EN : 0);
440
441 regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, SYS_CTRL0_FRM_RST_EN, 0);
442 regmap_write_bits(gvi->regmap, GVI_SYS_CTRL1, SYS_CTRL1_LANE_ALIGN_EN, 0);
443 }
444
rk628_gvi_post_enable(struct rk628_gvi * gvi)445 static void rk628_gvi_post_enable(struct rk628_gvi *gvi)
446 {
447 u32 val;
448
449 val = SYS_CTRL0_GVI_EN | SYS_CTRL0_AUTO_GATING;
450 regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, val, 3);
451 }
452
rk628_gvi_bridge_enable(struct drm_bridge * bridge)453 static void rk628_gvi_bridge_enable(struct drm_bridge *bridge)
454 {
455 struct rk628_gvi *gvi = bridge_to_gvi(bridge);
456 unsigned int rate = rk628_gvi_get_lane_rate(gvi);
457 int ret;
458
459 regmap_update_bits(gvi->grf, GRF_SYSTEM_CON0, SW_OUTPUT_MODE_MASK,
460 SW_OUTPUT_MODE(OUTPUT_MODE_GVI));
461 phy_set_bus_width(gvi->phy, rate);
462 rk628_combtxphy_set_gvi_division_mode(gvi->phy, gvi->division_mode);
463 ret = phy_set_mode(gvi->phy, 0);
464 if (ret) {
465 dev_err(gvi->dev, "failed to set phy mode: %d\n", ret);
466 return;
467 }
468 phy_power_on(gvi->phy);
469 gvi->lane_mbps = phy_get_bus_width(gvi->phy);
470 rk628_gvi_pre_enable(gvi);
471 drm_panel_prepare(gvi->panel);
472 rk628_gvi_enable_color_bar(gvi);
473 rk628_gvi_post_enable(gvi);
474 drm_panel_enable(gvi->panel);
475
476 dev_info(gvi->dev,
477 "GVI-Link bandwidth: %d x %d Mbps, Byte mode: %d, Color Depty: %d, %s division mode\n",
478 gvi->lane_mbps, gvi->lane_num, gvi->byte_mode,
479 gvi->color_depth, gvi->division_mode ? "two" : "one");
480 }
481
rk628_gvi_post_disable(struct drm_bridge * bridge)482 static void rk628_gvi_post_disable(struct drm_bridge *bridge)
483 {
484 struct rk628_gvi *gvi = bridge_to_gvi(bridge);
485
486 regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, SYS_CTRL0_GVI_EN, 0);
487 }
488
rk628_gvi_bridge_disable(struct drm_bridge * bridge)489 static void rk628_gvi_bridge_disable(struct drm_bridge *bridge)
490 {
491 struct rk628_gvi *gvi = bridge_to_gvi(bridge);
492
493 drm_panel_disable(gvi->panel);
494 drm_panel_unprepare(gvi->panel);
495 rk628_gvi_post_disable(bridge);
496 clk_disable_unprepare(gvi->pclk);
497 phy_power_off(gvi->phy);
498 }
499
rk628_gvi_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)500 static int rk628_gvi_bridge_attach(struct drm_bridge *bridge,
501 enum drm_bridge_attach_flags flags)
502 {
503 struct rk628_gvi *gvi = bridge_to_gvi(bridge);
504 struct drm_connector *connector = &gvi->connector;
505 struct drm_device *drm = bridge->dev;
506 int ret;
507
508 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
509 return 0;
510
511 ret = drm_connector_init(drm, connector, &rk628_gvi_connector_funcs,
512 DRM_MODE_CONNECTOR_LVDS);
513 if (ret) {
514 dev_err(gvi->dev, "Failed to initialize connector with drm\n");
515 return ret;
516 }
517
518 drm_connector_helper_add(connector, &rk628_gvi_connector_helper_funcs);
519 drm_connector_attach_encoder(connector, bridge->encoder);
520
521 return 0;
522 }
523
rk628_gvi_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adj)524 static void rk628_gvi_bridge_mode_set(struct drm_bridge *bridge,
525 const struct drm_display_mode *mode,
526 const struct drm_display_mode *adj)
527 {
528 struct rk628_gvi *gvi = bridge_to_gvi(bridge);
529
530 rk628_mode_copy(gvi->parent, &gvi->mode, mode);
531
532 dev_info(gvi->dev, "src mode: %dx%d, clk: %d, dst mode: %dx%d, clk: %d\n",
533 mode->hdisplay, mode->vdisplay, mode->clock,
534 gvi->mode.hdisplay, gvi->mode.vdisplay, gvi->mode.clock);
535 }
536
537 static const struct drm_bridge_funcs rk628_gvi_bridge_funcs = {
538 .attach = rk628_gvi_bridge_attach,
539 .enable = rk628_gvi_bridge_enable,
540 .disable = rk628_gvi_bridge_disable,
541 .mode_set = rk628_gvi_bridge_mode_set,
542 };
543
544 static const struct regmap_range rk628_gvi_readable_ranges[] = {
545 regmap_reg_range(GVI_SYS_CTRL0, GVI_COLOR_BAR_VTIMING1),
546 };
547
548 static const struct regmap_access_table rk628_gvi_readable_table = {
549 .yes_ranges = rk628_gvi_readable_ranges,
550 .n_yes_ranges = ARRAY_SIZE(rk628_gvi_readable_ranges),
551 };
552
553 static const struct regmap_config rk628_gvi_regmap_cfg = {
554 .name = "gvi",
555 .reg_bits = 32,
556 .val_bits = 32,
557 .reg_stride = 4,
558 .max_register = GVI_COLOR_BAR_VTIMING1,
559 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
560 .val_format_endian = REGMAP_ENDIAN_LITTLE,
561 .rd_table = &rk628_gvi_readable_table,
562 };
563
rk628_gvi_probe(struct platform_device * pdev)564 static int rk628_gvi_probe(struct platform_device *pdev)
565 {
566 struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
567 struct device *dev = &pdev->dev;
568 struct rk628_gvi *gvi;
569 int ret = 0;
570
571 if (!of_device_is_available(dev->of_node))
572 return -ENODEV;
573
574 gvi = devm_kzalloc(dev, sizeof(*gvi), GFP_KERNEL);
575 if (!gvi)
576 return -ENOMEM;
577
578 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
579 &gvi->panel, NULL);
580 if (ret)
581 return ret;
582
583 gvi->dev = dev;
584 gvi->parent = rk628;
585 gvi->division_mode = of_property_read_bool(dev->of_node,
586 "rockchip,division-mode");
587 ret = of_property_read_u32(dev->of_node, "rockchip,lane-num",
588 &gvi->lane_num);
589 if (ret) {
590 dev_err(gvi->dev, "Failed to get lane num\n");
591 gvi->lane_num = 4;
592 }
593
594 platform_set_drvdata(pdev, gvi);
595 gvi->grf = rk628->grf;
596 if (!gvi->grf)
597 return -ENODEV;
598
599 gvi->regmap = devm_regmap_init_i2c(rk628->client,
600 &rk628_gvi_regmap_cfg);
601 if (IS_ERR(gvi->regmap)) {
602 ret = PTR_ERR(gvi->regmap);
603 dev_err(dev, "failed to allocate register map: %d\n", ret);
604 return ret;
605 }
606
607 gvi->pclk = devm_clk_get(dev, "pclk");
608 if (IS_ERR(gvi->pclk)) {
609 ret = PTR_ERR(gvi->pclk);
610 dev_err(dev, "failed to get pclk: %d\n", ret);
611 return ret;
612 }
613
614 gvi->rst = of_reset_control_get(dev->of_node, NULL);
615 if (IS_ERR(gvi->rst)) {
616 ret = PTR_ERR(gvi->rst);
617 dev_err(dev, "failed to get reset control: %d\n", ret);
618 return ret;
619 }
620
621 gvi->phy = devm_of_phy_get(dev, dev->of_node, NULL);
622 if (IS_ERR(gvi->phy)) {
623 ret = PTR_ERR(gvi->phy);
624 dev_err(dev, "failed to get phy: %d\n", ret);
625 return ret;
626 }
627
628 gvi->base.funcs = &rk628_gvi_bridge_funcs;
629 gvi->base.of_node = dev->of_node;
630 drm_bridge_add(&gvi->base);
631
632 return 0;
633 }
634
rk628_gvi_remove(struct platform_device * pdev)635 static int rk628_gvi_remove(struct platform_device *pdev)
636 {
637 struct rk628_gvi *gvi = platform_get_drvdata(pdev);
638
639 drm_bridge_remove(&gvi->base);
640
641 return 0;
642 }
643
644 static const struct of_device_id rk628_gvi_of_match[] = {
645 {.compatible = "rockchip,rk628-gvi",},
646 {},
647 };
648
649 MODULE_DEVICE_TABLE(of, rk628_gvi_of_match);
650
651 static struct platform_driver rk628_gvi_driver = {
652 .driver = {
653 .name = "rk628-gvi",
654 .of_match_table = of_match_ptr(rk628_gvi_of_match),
655 },
656 .probe = rk628_gvi_probe,
657 .remove = rk628_gvi_remove,
658 };
659
660 module_platform_driver(rk628_gvi_driver);
661
662 MODULE_AUTHOR("Sandy Huang <hjc@rock-chips.com>");
663 MODULE_DESCRIPTION("Rockchip RK628 GVI driver");
664 MODULE_LICENSE("GPL v2");
665