1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Dingxian Wen <shawn.wen@rock-chips.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __RK628_CSI_H 9*4882a593Smuzhiyun #define __RK628_CSI_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "rk628.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CSITX_BASE 0x00040000 14*4882a593Smuzhiyun #define CSITX_CONFIG_DONE (CSITX_BASE + 0x0000) 15*4882a593Smuzhiyun #define CONFIG_DONE_IMD BIT(4) 16*4882a593Smuzhiyun #define CONFIG_DONE BIT(0) 17*4882a593Smuzhiyun #define CSITX_CSITX_EN (CSITX_BASE + 0x0004) 18*4882a593Smuzhiyun #define VOP_YU_SWAP_MASK BIT(14) 19*4882a593Smuzhiyun #define VOP_YU_SWAP(x) UPDATE(x, 14, 14) 20*4882a593Smuzhiyun #define VOP_UV_SWAP_MASK BIT(13) 21*4882a593Smuzhiyun #define VOP_UV_SWAP(x) UPDATE(x, 13, 13) 22*4882a593Smuzhiyun #define VOP_YUV422_EN_MASK BIT(12) 23*4882a593Smuzhiyun #define VOP_YUV422_EN(x) UPDATE(x, 12, 12) 24*4882a593Smuzhiyun #define VOP_P2_EN_MASK BIT(8) 25*4882a593Smuzhiyun #define VOP_P2_EN(x) UPDATE(x, 8, 8) 26*4882a593Smuzhiyun #define LANE_NUM_MASK GENMASK(5, 4) 27*4882a593Smuzhiyun #define LANE_NUM(x) UPDATE(x, 5, 4) 28*4882a593Smuzhiyun #define DPHY_EN_MASK BIT(2) 29*4882a593Smuzhiyun #define DPHY_EN(x) UPDATE(x, 2, 2) 30*4882a593Smuzhiyun #define CSITX_EN_MASK BIT(0) 31*4882a593Smuzhiyun #define CSITX_EN(x) UPDATE(x, 0, 0) 32*4882a593Smuzhiyun #define CSITX_CSITX_VERSION (CSITX_BASE + 0x0008) 33*4882a593Smuzhiyun #define CSITX_SYS_CTRL0_IMD (CSITX_BASE + 0x0010) 34*4882a593Smuzhiyun #define CSITX_SYS_CTRL1 (CSITX_BASE + 0x0014) 35*4882a593Smuzhiyun #define BYPASS_SELECT_MASK BIT(0) 36*4882a593Smuzhiyun #define BYPASS_SELECT(x) UPDATE(x, 0, 0) 37*4882a593Smuzhiyun #define CSITX_SYS_CTRL2 (CSITX_BASE + 0x0018) 38*4882a593Smuzhiyun #define VOP_WHOLE_FRM_EN BIT(5) 39*4882a593Smuzhiyun #define VSYNC_ENABLE BIT(0) 40*4882a593Smuzhiyun #define CSITX_SYS_CTRL3_IMD (CSITX_BASE + 0x001c) 41*4882a593Smuzhiyun #define CONT_MODE_CLK_CLR_MASK BIT(8) 42*4882a593Smuzhiyun #define CONT_MODE_CLK_CLR(x) UPDATE(x, 8, 8) 43*4882a593Smuzhiyun #define CONT_MODE_CLK_SET_MASK BIT(4) 44*4882a593Smuzhiyun #define CONT_MODE_CLK_SET(x) UPDATE(x, 4, 4) 45*4882a593Smuzhiyun #define NON_CONTINUOUS_MODE_MASK BIT(0) 46*4882a593Smuzhiyun #define NON_CONTINUOUS_MODE(x) UPDATE(x, 0, 0) 47*4882a593Smuzhiyun #define CSITX_TIMING_HPW_PADDING_NUM (CSITX_BASE + 0x0030) 48*4882a593Smuzhiyun #define CSITX_VOP_PATH_CTRL (CSITX_BASE + 0x0040) 49*4882a593Smuzhiyun #define VOP_WC_USERDEFINE_MASK GENMASK(31, 16) 50*4882a593Smuzhiyun #define VOP_WC_USERDEFINE(x) UPDATE(x, 31, 16) 51*4882a593Smuzhiyun #define VOP_DT_USERDEFINE_MASK GENMASK(13, 8) 52*4882a593Smuzhiyun #define VOP_DT_USERDEFINE(x) UPDATE(x, 13, 8) 53*4882a593Smuzhiyun #define VOP_PIXEL_FORMAT_MASK GENMASK(7, 4) 54*4882a593Smuzhiyun #define VOP_PIXEL_FORMAT(x) UPDATE(x, 7, 4) 55*4882a593Smuzhiyun #define VOP_WC_USERDEFINE_EN_MASK BIT(3) 56*4882a593Smuzhiyun #define VOP_WC_USERDEFINE_EN(x) UPDATE(x, 3, 3) 57*4882a593Smuzhiyun #define VOP_DT_USERDEFINE_EN_MASK BIT(1) 58*4882a593Smuzhiyun #define VOP_DT_USERDEFINE_EN(x) UPDATE(x, 1, 1) 59*4882a593Smuzhiyun #define VOP_PATH_EN_MASK BIT(0) 60*4882a593Smuzhiyun #define VOP_PATH_EN(x) UPDATE(x, 0, 0) 61*4882a593Smuzhiyun #define CSITX_VOP_PATH_PKT_CTRL (CSITX_BASE + 0x0050) 62*4882a593Smuzhiyun #define CSITX_CSITX_STATUS0 (CSITX_BASE + 0x0070) 63*4882a593Smuzhiyun #define CSITX_CSITX_STATUS1 (CSITX_BASE + 0x0074) 64*4882a593Smuzhiyun #define STOPSTATE_LANE3 BIT(7) 65*4882a593Smuzhiyun #define STOPSTATE_LANE2 BIT(6) 66*4882a593Smuzhiyun #define STOPSTATE_LANE1 BIT(5) 67*4882a593Smuzhiyun #define STOPSTATE_LANE0 BIT(4) 68*4882a593Smuzhiyun #define STOPSTATE_CLK BIT(1) 69*4882a593Smuzhiyun #define DPHY_PLL_LOCK BIT(0) 70*4882a593Smuzhiyun #define CSITX_ERR_INTR_EN_IMD (CSITX_BASE + 0x0090) 71*4882a593Smuzhiyun #define CSITX_ERR_INTR_CLR_IMD (CSITX_BASE + 0x0094) 72*4882a593Smuzhiyun #define CSITX_ERR_INTR_STATUS_IMD (CSITX_BASE + 0x0098) 73*4882a593Smuzhiyun #define CSITX_ERR_INTR_RAW_STATUS_IMD (CSITX_BASE + 0x009c) 74*4882a593Smuzhiyun #define CSITX_LPDT_DATA_IMD (CSITX_BASE + 0x00a8) 75*4882a593Smuzhiyun #define CSITX_DPHY_CTRL (CSITX_BASE + 0x00b0) 76*4882a593Smuzhiyun #define CSI_DPHY_EN_MASK GENMASK(7, 3) 77*4882a593Smuzhiyun #define CSI_DPHY_EN(x) UPDATE(x, 7, 3) 78*4882a593Smuzhiyun #define DPHY_ENABLECLK BIT(3) 79*4882a593Smuzhiyun #define CSI_MAX_REGISTER CSITX_DPHY_CTRL 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif 82