1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Shunqing Chen csq@rock-chips.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _RK628_COMBTXPHY_H 9*4882a593Smuzhiyun #define _RK628_COMBTXPHY_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define COMBTXPHY_BASE 0x90000 12*4882a593Smuzhiyun #define COMBTXPHY_REG(x) ((x) + COMBTXPHY_BASE) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define COMBTXPHY_CON0 COMBTXPHY_REG(0x0000) 15*4882a593Smuzhiyun #define SW_TX_IDLE_MASK GENMASK(29, 20) 16*4882a593Smuzhiyun #define SW_TX_IDLE(x) UPDATE(x, 29, 20) 17*4882a593Smuzhiyun #define SW_TX_PD_MASK GENMASK(17, 8) 18*4882a593Smuzhiyun #define SW_TX_PD(x) UPDATE(x, 17, 8) 19*4882a593Smuzhiyun #define SW_BUS_WIDTH_MASK GENMASK(6, 5) 20*4882a593Smuzhiyun #define SW_BUS_WIDTH_7BIT UPDATE(0x3, 6, 5) 21*4882a593Smuzhiyun #define SW_BUS_WIDTH_8BIT UPDATE(0x2, 6, 5) 22*4882a593Smuzhiyun #define SW_BUS_WIDTH_9BIT UPDATE(0x1, 6, 5) 23*4882a593Smuzhiyun #define SW_BUS_WIDTH_10BIT UPDATE(0x0, 6, 5) 24*4882a593Smuzhiyun #define SW_PD_PLL_MASK BIT(4) 25*4882a593Smuzhiyun #define SW_PD_PLL BIT(4) 26*4882a593Smuzhiyun #define SW_GVI_LVDS_EN_MASK BIT(3) 27*4882a593Smuzhiyun #define SW_GVI_LVDS_EN BIT(3) 28*4882a593Smuzhiyun #define SW_MIPI_DSI_EN_MASK BIT(2) 29*4882a593Smuzhiyun #define SW_MIPI_DSI_EN BIT(2) 30*4882a593Smuzhiyun #define SW_MODULEB_EN_MASK BIT(1) 31*4882a593Smuzhiyun #define SW_MODULEB_EN BIT(1) 32*4882a593Smuzhiyun #define SW_MODULEA_EN_MASK BIT(0) 33*4882a593Smuzhiyun #define SW_MODULEA_EN BIT(0) 34*4882a593Smuzhiyun #define COMBTXPHY_CON1 COMBTXPHY_REG(0x0004) 35*4882a593Smuzhiyun #define COMBTXPHY_CON2 COMBTXPHY_REG(0x0008) 36*4882a593Smuzhiyun #define COMBTXPHY_CON3 COMBTXPHY_REG(0x000c) 37*4882a593Smuzhiyun #define COMBTXPHY_CON4 COMBTXPHY_REG(0x0010) 38*4882a593Smuzhiyun #define COMBTXPHY_CON5 COMBTXPHY_REG(0x0014) 39*4882a593Smuzhiyun #define SW_RATE(x) UPDATE(x, 26, 24) 40*4882a593Smuzhiyun #define SW_REF_DIV(x) UPDATE(x, 20, 16) 41*4882a593Smuzhiyun #define SW_PLL_FB_DIV(x) UPDATE(x, 14, 10) 42*4882a593Smuzhiyun #define SW_PLL_FRAC_DIV(x) UPDATE(x, 9, 0) 43*4882a593Smuzhiyun #define COMBTXPHY_CON6 COMBTXPHY_REG(0x0018) 44*4882a593Smuzhiyun #define COMBTXPHY_CON7 COMBTXPHY_REG(0x001c) 45*4882a593Smuzhiyun #define SW_TX_RTERM_MASK GENMASK(22, 20) 46*4882a593Smuzhiyun #define SW_TX_RTERM(x) UPDATE(x, 22, 20) 47*4882a593Smuzhiyun #define SW_TX_MODE_MASK GENMASK(17, 16) 48*4882a593Smuzhiyun #define SW_TX_MODE(x) UPDATE(x, 17, 16) 49*4882a593Smuzhiyun #define SW_TX_CTL_CON5_MASK BIT(10) 50*4882a593Smuzhiyun #define SW_TX_CTL_CON5(x) UPDATE(x, 10, 10) 51*4882a593Smuzhiyun #define SW_TX_CTL_CON4_MASK GENMASK(9, 8) 52*4882a593Smuzhiyun #define SW_TX_CTL_CON4(x) UPDATE(x, 9, 8) 53*4882a593Smuzhiyun #define COMBTXPHY_CON8 COMBTXPHY_REG(0x0020) 54*4882a593Smuzhiyun #define COMBTXPHY_CON9 COMBTXPHY_REG(0x0024) 55*4882a593Smuzhiyun #define SW_DSI_FSET_EN_MASK BIT(29) 56*4882a593Smuzhiyun #define SW_DSI_FSET_EN BIT(29) 57*4882a593Smuzhiyun #define SW_DSI_RCAL_EN_MASK BIT(28) 58*4882a593Smuzhiyun #define SW_DSI_RCAL_EN BIT(28) 59*4882a593Smuzhiyun #define COMBTXPHY_CON10 COMBTXPHY_REG(0x0028) 60*4882a593Smuzhiyun #define TX9_CKDRV_EN BIT(9) 61*4882a593Smuzhiyun #define TX8_CKDRV_EN BIT(8) 62*4882a593Smuzhiyun #define TX7_CKDRV_EN BIT(7) 63*4882a593Smuzhiyun #define TX6_CKDRV_EN BIT(6) 64*4882a593Smuzhiyun #define TX5_CKDRV_EN BIT(5) 65*4882a593Smuzhiyun #define TX4_CKDRV_EN BIT(4) 66*4882a593Smuzhiyun #define TX3_CKDRV_EN BIT(3) 67*4882a593Smuzhiyun #define TX2_CKDRV_EN BIT(2) 68*4882a593Smuzhiyun #define TX1_CKDRV_EN BIT(1) 69*4882a593Smuzhiyun #define TX0_CKDRV_EN BIT(0) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun enum phy_mode { 72*4882a593Smuzhiyun PHY_MODE_INVALID, 73*4882a593Smuzhiyun PHY_MODE_VIDEO_MIPI, 74*4882a593Smuzhiyun PHY_MODE_VIDEO_LVDS, 75*4882a593Smuzhiyun PHY_MODE_VIDEO_GVI, 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct rk628_combtxphy { 79*4882a593Smuzhiyun enum phy_mode mode; 80*4882a593Smuzhiyun unsigned int flags; 81*4882a593Smuzhiyun u8 ref_div; 82*4882a593Smuzhiyun u8 fb_div; 83*4882a593Smuzhiyun u16 frac_div; 84*4882a593Smuzhiyun u8 rate_div; 85*4882a593Smuzhiyun u32 bus_width; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun void rk628_txphy_set_mode(struct rk628 *rk628, enum phy_mode mode); 89*4882a593Smuzhiyun void rk628_txphy_set_bus_width(struct rk628 *rk628, u32 bus_width); 90*4882a593Smuzhiyun u32 rk628_txphy_get_bus_width(struct rk628 *rk628); 91*4882a593Smuzhiyun void rk628_txphy_power_on(struct rk628 *rk628); 92*4882a593Smuzhiyun void rk628_txphy_power_off(struct rk628 *rk628); 93*4882a593Smuzhiyun struct rk628_combtxphy *rk628_txphy_register(struct rk628 *rk628); 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #endif 96