1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Chen Shunqing <csq@rock-chips.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef RK628_CSI_H 9*4882a593Smuzhiyun #define RK628_CSI_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "rk628.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CSI_REG(x) ((x) + 0x40000) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CSITX_CONFIG_DONE CSI_REG(0x0000) 16*4882a593Smuzhiyun #define CONFIG_DONE_IMD BIT(4) 17*4882a593Smuzhiyun #define CONFIG_DONE BIT(0) 18*4882a593Smuzhiyun #define CSITX_CSITX_EN CSI_REG(0x0004) 19*4882a593Smuzhiyun #define VOP_YU_SWAP_MASK BIT(14) 20*4882a593Smuzhiyun #define VOP_YU_SWAP(x) UPDATE(x, 14, 14) 21*4882a593Smuzhiyun #define VOP_UV_SWAP_MASK BIT(13) 22*4882a593Smuzhiyun #define VOP_UV_SWAP(x) UPDATE(x, 13, 13) 23*4882a593Smuzhiyun #define VOP_YUV422_EN_MASK BIT(12) 24*4882a593Smuzhiyun #define VOP_YUV422_EN(x) UPDATE(x, 12, 12) 25*4882a593Smuzhiyun #define VOP_P2_EN_MASK BIT(8) 26*4882a593Smuzhiyun #define VOP_P2_EN(x) UPDATE(x, 8, 8) 27*4882a593Smuzhiyun #define LANE_NUM_MASK GENMASK(5, 4) 28*4882a593Smuzhiyun #define LANE_NUM(x) UPDATE(x, 5, 4) 29*4882a593Smuzhiyun #define DPHY_EN_MASK BIT(2) 30*4882a593Smuzhiyun #define DPHY_EN(x) UPDATE(x, 2, 2) 31*4882a593Smuzhiyun #define CSITX_EN_MASK BIT(0) 32*4882a593Smuzhiyun #define CSITX_EN(x) UPDATE(x, 0, 0) 33*4882a593Smuzhiyun #define CSITX_CSITX_VERSION CSI_REG(0x0008) 34*4882a593Smuzhiyun #define CSITX_SYS_CTRL0_IMD CSI_REG(0x0010) 35*4882a593Smuzhiyun #define CSITX_SYS_CTRL1 CSI_REG(0x0014) 36*4882a593Smuzhiyun #define BYPASS_SELECT_MASK BIT(0) 37*4882a593Smuzhiyun #define BYPASS_SELECT(x) UPDATE(x, 0, 0) 38*4882a593Smuzhiyun #define CSITX_SYS_CTRL2 CSI_REG(0x0018) 39*4882a593Smuzhiyun #define VOP_WHOLE_FRM_EN BIT(5) 40*4882a593Smuzhiyun #define VSYNC_ENABLE BIT(0) 41*4882a593Smuzhiyun #define CSITX_SYS_CTRL3_IMD CSI_REG(0x001c) 42*4882a593Smuzhiyun #define CONT_MODE_CLK_CLR_MASK BIT(8) 43*4882a593Smuzhiyun #define CONT_MODE_CLK_CLR(x) UPDATE(x, 8, 8) 44*4882a593Smuzhiyun #define CONT_MODE_CLK_SET_MASK BIT(4) 45*4882a593Smuzhiyun #define CONT_MODE_CLK_SET(x) UPDATE(x, 4, 4) 46*4882a593Smuzhiyun #define NON_CONTINOUS_MODE_MASK BIT(0) 47*4882a593Smuzhiyun #define NON_CONTINOUS_MODE(x) UPDATE(x, 0, 0) 48*4882a593Smuzhiyun #define CSITX_TIMING_HPW_PADDING_NUM CSI_REG(0x0030) 49*4882a593Smuzhiyun #define CSITX_VOP_PATH_CTRL CSI_REG(0x0040) 50*4882a593Smuzhiyun #define VOP_WC_USERDEFINE_MASK GENMASK(31, 16) 51*4882a593Smuzhiyun #define VOP_WC_USERDEFINE(x) UPDATE(x, 31, 16) 52*4882a593Smuzhiyun #define VOP_DT_USERDEFINE_MASK GENMASK(13, 8) 53*4882a593Smuzhiyun #define VOP_DT_USERDEFINE(x) UPDATE(x, 13, 8) 54*4882a593Smuzhiyun #define VOP_PIXEL_FORMAT_MASK GENMASK(7, 4) 55*4882a593Smuzhiyun #define VOP_PIXEL_FORMAT(x) UPDATE(x, 7, 4) 56*4882a593Smuzhiyun #define VOP_WC_USERDEFINE_EN_MASK BIT(3) 57*4882a593Smuzhiyun #define VOP_WC_USERDEFINE_EN(x) UPDATE(x, 3, 3) 58*4882a593Smuzhiyun #define VOP_DT_USERDEFINE_EN_MASK BIT(1) 59*4882a593Smuzhiyun #define VOP_DT_USERDEFINE_EN(x) UPDATE(x, 1, 1) 60*4882a593Smuzhiyun #define VOP_PATH_EN_MASK BIT(0) 61*4882a593Smuzhiyun #define VOP_PATH_EN(x) UPDATE(x, 0, 0) 62*4882a593Smuzhiyun #define CSITX_VOP_PATH_PKT_CTRL CSI_REG(0x0050) 63*4882a593Smuzhiyun #define CSITX_CSITX_STATUS0 CSI_REG(0x0070) 64*4882a593Smuzhiyun #define CSITX_CSITX_STATUS1 CSI_REG(0x0074) 65*4882a593Smuzhiyun #define STOPSTATE_LANE3 BIT(7) 66*4882a593Smuzhiyun #define STOPSTATE_LANE2 BIT(6) 67*4882a593Smuzhiyun #define STOPSTATE_LANE1 BIT(5) 68*4882a593Smuzhiyun #define STOPSTATE_LANE0 BIT(4) 69*4882a593Smuzhiyun #define STOPSTATE_CLK BIT(1) 70*4882a593Smuzhiyun #define DPHY_PLL_LOCK BIT(0) 71*4882a593Smuzhiyun #define CSITX_ERR_INTR_EN_IMD CSI_REG(0x0090) 72*4882a593Smuzhiyun #define CSITX_ERR_INTR_CLR_IMD CSI_REG(0x0094) 73*4882a593Smuzhiyun #define CSITX_ERR_INTR_STATUS_IMD CSI_REG(0x0098) 74*4882a593Smuzhiyun #define CSITX_ERR_INTR_RAW_STATUS_IMD CSI_REG(0x009c) 75*4882a593Smuzhiyun #define CSITX_LPDT_DATA_IMD CSI_REG(0x00a8) 76*4882a593Smuzhiyun #define CSITX_DPHY_CTRL CSI_REG(0x00b0) 77*4882a593Smuzhiyun #define CSI_DPHY_EN_MASK GENMASK(7, 3) 78*4882a593Smuzhiyun #define CSI_DPHY_EN(x) UPDATE(x, 7, 3) 79*4882a593Smuzhiyun #define DPHY_ENABLECLK BIT(3) 80*4882a593Smuzhiyun #define CSI_MAX_REGISTER CSITX_DPHY_CTRL 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun void rk628_csi_init(struct rk628 *rk628); 83*4882a593Smuzhiyun void rk628_csi_enable(struct rk628 *rk628); 84*4882a593Smuzhiyun void rk628_csi_disable(struct rk628 *rk628); 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif 87