| /OK3568_Linux_fs/kernel/arch/arm/mach-prima2/ |
| H A D | Kconfig | 3 bool "CSR SiRF"
14 Support for CSR SiRFprimaII/Marco/Polo platforms
18 comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features"
21 bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
25 Support for CSR SiRFSoC ARM Cortex A9 Platform
28 bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform"
34 Support for CSR SiRFSoC ARM Cortex A7 Platform
37 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
43 Support for CSR SiRFSoC ARM Cortex A9 Platform
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| /OK3568_Linux_fs/kernel/drivers/scsi/aacraid/ |
| H A D | aacraid.h | 1082 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1083 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1084 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) argument
1085 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) argument
1144 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) argument
1145 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) argument
1146 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) argument
1147 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) argument
1162 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) argument
1163 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) argument
[all …]
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | prima2-evb.dts | 3 * DTS file for CSR SiRFprimaII Evaluation Board
5 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
13 model = "CSR SiRFprimaII Evaluation Board";
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| H A D | atlas6-evb.dts | 3 * DTS file for CSR SiRFatlas6 Evaluation Board
5 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
13 model = "CSR SiRFatlas6 Evaluation Board";
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| H A D | atlas7-evb.dts | 3 * DTS file for CSR SiRFatlas7 Evaluation Board
5 * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
16 model = "CSR SiRFatlas7 Evaluation Board";
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| /OK3568_Linux_fs/kernel/arch/c6x/kernel/ |
| H A D | entry.S | 28 MVC .S2 CSR,reg
30 MVC .S2 reg,CSR
34 MVC .S2 CSR,reg
36 MVC .S2 reg,CSR
74 || MVC .S2 CSR,B12
111 STDW .D2T2 B13:B12,*SP--[1] ; save PC and CSR
127 LDDW .D2T2 *++SP[1],B13:B12 ; get PC (B13) and CSR (B12)
167 || MVC .S2 B12,CSR
245 MVC .S2 CSR,B1
247 MVC .S2 B1,CSR ; enable ints
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| H A D | head.S | 42 MVC .S2 CSR,B2
44 MVC .S2 B2,CSR
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| /OK3568_Linux_fs/kernel/drivers/dma/ |
| H A D | txx9dmac.c | 296 channel64_readl(dc, CSR)); in txx9dmac_dump_regs()
308 channel32_readl(dc, CSR)); in txx9dmac_dump_regs()
339 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { in txx9dmac_dostart()
349 channel64_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
370 channel32_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
519 channel_writel(dc, CSR, errors); in txx9dmac_handle_error()
545 csr = channel64_readl(dc, CSR); in txx9dmac_scan_descriptors()
546 channel64_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
[all …]
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| H A D | txx9dmac.h | 78 TXX9_DMA_REG32(CSR); /* Channel Status Register */
88 u32 CSR; member
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ |
| H A D | xgene.txt | 36 - reg : shall be a list of address and length pairs describing the CSR
49 - csr-offset : Offset to the CSR reset register from the reset address base.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
55 - divider-offset : Offset to the divider CSR register from the divider base.
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| H A D | prima2-clock.txt | 1 * Clock bindings for CSR SiRFprimaII
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| H A D | csr,atlas7-car.txt | 1 * Clock and reset bindings for CSR atlas7
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| /OK3568_Linux_fs/kernel/drivers/staging/qlge/ |
| H A D | qlge_mpi.c | 9 tmp = ql_read32(qdev, CSR); in ql_unpause_mpi_risc()
13 ql_write32(qdev, CSR, CSR_CMD_CLR_PAUSE); in ql_unpause_mpi_risc()
23 ql_write32(qdev, CSR, CSR_CMD_SET_PAUSE); in ql_pause_mpi_risc()
25 tmp = ql_read32(qdev, CSR); in ql_pause_mpi_risc()
39 ql_write32(qdev, CSR, CSR_CMD_SET_RST); in ql_hard_reset_mpi_risc()
41 tmp = ql_read32(qdev, CSR); in ql_hard_reset_mpi_risc()
43 ql_write32(qdev, CSR, CSR_CMD_CLR_RST); in ql_hard_reset_mpi_risc()
170 if (ql_read32(qdev, CSR) & CSR_HRI) in ql_exec_mb_cmd()
189 ql_write32(qdev, CSR, CSR_CMD_SET_H2R_INT); in ql_exec_mb_cmd()
513 ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT); in ql_mpi_handler()
[all …]
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| /OK3568_Linux_fs/external/security/rk_tee_user/v2/cert/ |
| H A D | README.txt | 9 #Mid CSR and key
15 #My CSR and key
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| /OK3568_Linux_fs/kernel/arch/arm/plat-omap/ |
| H A D | dma.c | 411 p->dma_read(CSR, lch); in omap_enable_channel_irq()
413 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); in omap_enable_channel_irq()
425 p->dma_read(CSR, lch); in omap_disable_channel_irq()
427 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); in omap_disable_channel_irq()
821 csr = p->dma_read(CSR, ch); in omap1_dma_handle_ch()
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| /OK3568_Linux_fs/kernel/arch/arm/mach-omap1/ |
| H A D | dma.c | 59 [CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
219 l = dma_read(CSR, lch); in omap1_clear_dma()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/ |
| H A D | altera-pcie-msi.txt | 8 "csr": CSR registers
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio-atlas7.txt | 1 CSR SiRFatlas7 GPIO controller bindings
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/serial/ |
| H A D | sirf-uart.txt | 1 * CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter *
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/ |
| H A D | sirfsoc-dma.txt | 1 * CSR SiRFSoC DMA controller
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/reset/ |
| H A D | sirf,rstc.txt | 1 CSR SiRFSoC Reset Controller
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/misc/ |
| H A D | idt_89hpesx.txt | 1 EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices
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| /OK3568_Linux_fs/kernel/arch/arm/mach-omap2/ |
| H A D | dma.c | 56 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/ |
| H A D | spi-sirf.txt | 1 * CSR SiRFprimaII Serial Peripheral Interface
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/ |
| H A D | pinctrl-sirf.txt | 1 CSR SiRFprimaII pinmux controller
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