1*4882a593Smuzhiyun* Clock bindings for CSR SiRFprimaII 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "sirf,prima2-clkc" 5*4882a593Smuzhiyun- reg: Address and length of the register set 6*4882a593Smuzhiyun- interrupts: Should contain clock controller interrupt 7*4882a593Smuzhiyun- #clock-cells: Should be <1> 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThe clock consumer should specify the desired clock by having the clock 10*4882a593SmuzhiyunID in its "clocks" phandle cell. The following is a full list of prima2 11*4882a593Smuzhiyunclocks and IDs. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun Clock ID 14*4882a593Smuzhiyun --------------------------- 15*4882a593Smuzhiyun rtc 0 16*4882a593Smuzhiyun osc 1 17*4882a593Smuzhiyun pll1 2 18*4882a593Smuzhiyun pll2 3 19*4882a593Smuzhiyun pll3 4 20*4882a593Smuzhiyun mem 5 21*4882a593Smuzhiyun sys 6 22*4882a593Smuzhiyun security 7 23*4882a593Smuzhiyun dsp 8 24*4882a593Smuzhiyun gps 9 25*4882a593Smuzhiyun mf 10 26*4882a593Smuzhiyun io 11 27*4882a593Smuzhiyun cpu 12 28*4882a593Smuzhiyun uart0 13 29*4882a593Smuzhiyun uart1 14 30*4882a593Smuzhiyun uart2 15 31*4882a593Smuzhiyun tsc 16 32*4882a593Smuzhiyun i2c0 17 33*4882a593Smuzhiyun i2c1 18 34*4882a593Smuzhiyun spi0 19 35*4882a593Smuzhiyun spi1 20 36*4882a593Smuzhiyun pwmc 21 37*4882a593Smuzhiyun efuse 22 38*4882a593Smuzhiyun pulse 23 39*4882a593Smuzhiyun dmac0 24 40*4882a593Smuzhiyun dmac1 25 41*4882a593Smuzhiyun nand 26 42*4882a593Smuzhiyun audio 27 43*4882a593Smuzhiyun usp0 28 44*4882a593Smuzhiyun usp1 29 45*4882a593Smuzhiyun usp2 30 46*4882a593Smuzhiyun vip 31 47*4882a593Smuzhiyun gfx 32 48*4882a593Smuzhiyun mm 33 49*4882a593Smuzhiyun lcd 34 50*4882a593Smuzhiyun vpp 35 51*4882a593Smuzhiyun mmc01 36 52*4882a593Smuzhiyun mmc23 37 53*4882a593Smuzhiyun mmc45 38 54*4882a593Smuzhiyun usbpll 39 55*4882a593Smuzhiyun usb0 40 56*4882a593Smuzhiyun usb1 41 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunExamples: 59*4882a593Smuzhiyun 60*4882a593Smuzhiyunclks: clock-controller@88000000 { 61*4882a593Smuzhiyun compatible = "sirf,prima2-clkc"; 62*4882a593Smuzhiyun reg = <0x88000000 0x1000>; 63*4882a593Smuzhiyun interrupts = <3>; 64*4882a593Smuzhiyun #clock-cells = <1>; 65*4882a593Smuzhiyun}; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyuni2c0: i2c@b00e0000 { 68*4882a593Smuzhiyun cell-index = <0>; 69*4882a593Smuzhiyun compatible = "sirf,prima2-i2c"; 70*4882a593Smuzhiyun reg = <0xb00e0000 0x10000>; 71*4882a593Smuzhiyun interrupts = <24>; 72*4882a593Smuzhiyun clocks = <&clks 17>; 73*4882a593Smuzhiyun}; 74