1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * DTS file for CSR SiRFatlas6 Evaluation Board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/include/ "atlas6.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "CSR SiRFatlas6 Evaluation Board"; 14*4882a593Smuzhiyun compatible = "sirf,atlas6-cb", "sirf,atlas6"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun memory { 17*4882a593Smuzhiyun device_type = "memory"; 18*4882a593Smuzhiyun reg = <0x00000000 0x20000000>; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun axi { 22*4882a593Smuzhiyun peri-iobg { 23*4882a593Smuzhiyun uart@b0060000 { 24*4882a593Smuzhiyun pinctrl-names = "default"; 25*4882a593Smuzhiyun pinctrl-0 = <&uart1_pins_a>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun spi@b00d0000 { 28*4882a593Smuzhiyun status = "okay"; 29*4882a593Smuzhiyun pinctrl-names = "default"; 30*4882a593Smuzhiyun pinctrl-0 = <&spi0_pins_a>; 31*4882a593Smuzhiyun spi@0 { 32*4882a593Smuzhiyun compatible = "spidev"; 33*4882a593Smuzhiyun reg = <0>; 34*4882a593Smuzhiyun spi-max-frequency = <1000000>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun spi@b0170000 { 38*4882a593Smuzhiyun pinctrl-names = "default"; 39*4882a593Smuzhiyun pinctrl-0 = <&spi1_pins_a>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun i2c0: i2c@b00e0000 { 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun pinctrl-names = "default"; 44*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins_a>; 45*4882a593Smuzhiyun lcd@40 { 46*4882a593Smuzhiyun compatible = "sirf,lcd"; 47*4882a593Smuzhiyun reg = <0x40>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun disp-iobg { 53*4882a593Smuzhiyun lcd@90010000 { 54*4882a593Smuzhiyun status = "okay"; 55*4882a593Smuzhiyun pinctrl-names = "default"; 56*4882a593Smuzhiyun pinctrl-0 = <&lcd_24pins_a>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun display: display@0 { 61*4882a593Smuzhiyun panels { 62*4882a593Smuzhiyun panel0: panel@0 { 63*4882a593Smuzhiyun panel-name = "Innolux TFT"; 64*4882a593Smuzhiyun hactive = <800>; 65*4882a593Smuzhiyun vactive = <480>; 66*4882a593Smuzhiyun left_margin = <20>; 67*4882a593Smuzhiyun right_margin = <234>; 68*4882a593Smuzhiyun upper_margin = <3>; 69*4882a593Smuzhiyun lower_margin = <41>; 70*4882a593Smuzhiyun hsync_len = <3>; 71*4882a593Smuzhiyun vsync_len = <2>; 72*4882a593Smuzhiyun pixclock = <33264000>; 73*4882a593Smuzhiyun sync = <3>; 74*4882a593Smuzhiyun timing = <0x88>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun}; 79