1*4882a593Smuzhiyun* CSR SiRFSoC DMA controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunSee dma.txt first 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun- compatible: Should be "sirf,prima2-dmac", "sirf,atlas7-dmac" or 7*4882a593Smuzhiyun "sirf,atlas7-dmac-v2" 8*4882a593Smuzhiyun- reg: Should contain DMA registers location and length. 9*4882a593Smuzhiyun- interrupts: Should contain one interrupt shared by all channel 10*4882a593Smuzhiyun- #dma-cells: must be <1>. used to represent the number of integer 11*4882a593Smuzhiyun cells in the dmas property of client device. 12*4882a593Smuzhiyun- clocks: clock required 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunExample: 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunController: 17*4882a593Smuzhiyundmac0: dma-controller@b00b0000 { 18*4882a593Smuzhiyun compatible = "sirf,prima2-dmac"; 19*4882a593Smuzhiyun reg = <0xb00b0000 0x10000>; 20*4882a593Smuzhiyun interrupts = <12>; 21*4882a593Smuzhiyun clocks = <&clks 24>; 22*4882a593Smuzhiyun #dma-cells = <1>; 23*4882a593Smuzhiyun}; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunClient: 27*4882a593SmuzhiyunFill the specific dma request line in dmas. In the below example, spi0 read 28*4882a593Smuzhiyunchannel request line is 9 of the 2nd dma controller, while write channel uses 29*4882a593Smuzhiyun4 of the 2nd dma controller; spi1 read channel request line is 12 of the 1st 30*4882a593Smuzhiyundma controller, while write channel uses 13 of the 1st dma controller: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunspi0: spi@b00d0000 { 33*4882a593Smuzhiyun compatible = "sirf,prima2-spi"; 34*4882a593Smuzhiyun dmas = <&dmac1 9>, 35*4882a593Smuzhiyun <&dmac1 4>; 36*4882a593Smuzhiyun dma-names = "rx", "tx"; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyunspi1: spi@b0170000 { 40*4882a593Smuzhiyun compatible = "sirf,prima2-spi"; 41*4882a593Smuzhiyun dmas = <&dmac0 12>, 42*4882a593Smuzhiyun <&dmac0 13>; 43*4882a593Smuzhiyun dma-names = "rx", "tx"; 44*4882a593Smuzhiyun}; 45