1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyunmenuconfig ARCH_SIRF 3*4882a593Smuzhiyun bool "CSR SiRF" 4*4882a593Smuzhiyun depends on ARCH_MULTI_V7 5*4882a593Smuzhiyun select ARCH_HAS_RESET_CONTROLLER 6*4882a593Smuzhiyun select RESET_CONTROLLER 7*4882a593Smuzhiyun select GENERIC_IRQ_CHIP 8*4882a593Smuzhiyun select GPIOLIB 9*4882a593Smuzhiyun select NO_IOPORT_MAP 10*4882a593Smuzhiyun select REGMAP 11*4882a593Smuzhiyun select PINCTRL 12*4882a593Smuzhiyun select PINCTRL_SIRF 13*4882a593Smuzhiyun help 14*4882a593Smuzhiyun Support for CSR SiRFprimaII/Marco/Polo platforms 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunif ARCH_SIRF 17*4882a593Smuzhiyun 18*4882a593Smuzhiyuncomment "CSR SiRF atlas6/primaII/Atlas7 Specific Features" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunconfig ARCH_ATLAS6 21*4882a593Smuzhiyun bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform" 22*4882a593Smuzhiyun default y 23*4882a593Smuzhiyun select SIRF_IRQ 24*4882a593Smuzhiyun help 25*4882a593Smuzhiyun Support for CSR SiRFSoC ARM Cortex A9 Platform 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunconfig ARCH_ATLAS7 28*4882a593Smuzhiyun bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform" 29*4882a593Smuzhiyun default y 30*4882a593Smuzhiyun select ARM_GIC 31*4882a593Smuzhiyun select ATLAS7_TIMER 32*4882a593Smuzhiyun select HAVE_ARM_SCU if SMP 33*4882a593Smuzhiyun help 34*4882a593Smuzhiyun Support for CSR SiRFSoC ARM Cortex A7 Platform 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunconfig ARCH_PRIMA2 37*4882a593Smuzhiyun bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" 38*4882a593Smuzhiyun default y 39*4882a593Smuzhiyun select SIRF_IRQ 40*4882a593Smuzhiyun select ZONE_DMA 41*4882a593Smuzhiyun select PRIMA2_TIMER 42*4882a593Smuzhiyun help 43*4882a593Smuzhiyun Support for CSR SiRFSoC ARM Cortex A9 Platform 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunconfig SIRF_IRQ 46*4882a593Smuzhiyun bool 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunendif 49