1*4882a593Smuzhiyun* Altera PCIe MSI controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: should contain "altr,msi-1.0" 5*4882a593Smuzhiyun- reg: specifies the physical base address of the controller and 6*4882a593Smuzhiyun the length of the memory mapped region. 7*4882a593Smuzhiyun- reg-names: must include the following entries: 8*4882a593Smuzhiyun "csr": CSR registers 9*4882a593Smuzhiyun "vector_slave": vectors slave port region 10*4882a593Smuzhiyun- interrupts: specifies the interrupt source of the parent interrupt 11*4882a593Smuzhiyun controller. The format of the interrupt specifier depends on the 12*4882a593Smuzhiyun parent interrupt controller. 13*4882a593Smuzhiyun- num-vectors: number of vectors, range 1 to 32. 14*4882a593Smuzhiyun- msi-controller: indicates that this is MSI controller node 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample 18*4882a593Smuzhiyunmsi0: msi@0xFF200000 { 19*4882a593Smuzhiyun compatible = "altr,msi-1.0"; 20*4882a593Smuzhiyun reg = <0xFF200000 0x00000010 21*4882a593Smuzhiyun 0xFF200010 0x00000080>; 22*4882a593Smuzhiyun reg-names = "csr", "vector_slave"; 23*4882a593Smuzhiyun interrupt-parent = <&hps_0_arm_gic_0>; 24*4882a593Smuzhiyun interrupts = <0 42 4>; 25*4882a593Smuzhiyun msi-controller; 26*4882a593Smuzhiyun num-vectors = <32>; 27*4882a593Smuzhiyun}; 28