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Searched refs:CLK_SDMMC0 (Results 1 – 16 of 16) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/clk/zte/
H A Dclk-zx296702.c48 #define CLK_SDMMC0 (lsp1crpm_base + 0x2c) macro
708 ARRAY_SIZE(sdmmc0_wclk_sel), CLK_SDMMC0, 4, 1); in zx296702_lsp1_clocks_init()
710 zx_div("sdmmc0_wclk_div", "sdmmc0_wclk_mux", CLK_SDMMC0, 12, 4); in zx296702_lsp1_clocks_init()
712 zx_gate("sdmmc0_wclk", "sdmmc0_wclk_div", CLK_SDMMC0, 1); in zx296702_lsp1_clocks_init()
714 zx_gate("sdmmc0_pclk", "lsp1_apb_pclk", CLK_SDMMC0, 0); in zx296702_lsp1_clocks_init()
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dexynos5250.h83 #define CLK_SDMMC0 280 macro
H A Dexynos4.h135 #define CLK_SDMMC0 297 macro
H A Dexynos3250.h205 #define CLK_SDMMC0 199 macro
H A Drk3568-cru.h240 #define CLK_SDMMC0 177 macro
/OK3568_Linux_fs/u-boot/include/dt-bindings/clock/
H A Drk3568-cru.h240 #define CLK_SDMMC0 177 macro
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3568.c1425 case CLK_SDMMC0: in rk3568_sdmmc_get_clk()
1493 case CLK_SDMMC0: in rk3568_sdmmc_set_clk()
2578 case CLK_SDMMC0: in rk3568_clk_get_rate()
2764 case CLK_SDMMC0: in rk3568_clk_set_rate()
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-exynos5250.c561 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
H A Dclk-exynos3250.c645 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
H A Dclk-exynos4.c839 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dexynos3250.dtsi371 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
H A Dexynos4.dtsi323 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
H A Dexynos5250.dtsi538 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-rk3568.c912 COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0,
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3568.dtsi1819 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi2585 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,