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Searched refs:BIT_9 (Results 1 – 18 of 18) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/net/ethernet/realtek/r8168/
H A Dr8168_dash.h170 #define OCP_REG_CONFIG0_OOB_WDT BIT_9
190 #define TXS_UNF BIT_9
H A Dr8168_n.c3169 if (!(rtl8168_mac_ocp_read(tp, 0xDC04) & BIT_9)) in rtl8168_is_gpio_low()
3856 csi_tmp |= (BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12); in rtl8168_enable_exit_l1_mask()
3866 csi_tmp |= (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12); in rtl8168_enable_exit_l1_mask()
3883 csi_tmp &= ~(BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12); in rtl8168_disable_exit_l1_mask()
3893 csi_tmp &= ~(BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12); in rtl8168_disable_exit_l1_mask()
4200 if (RTL_R16(tp, 0xD2) & BIT_9) in rtl8168_wait_ll_share_fifo_ready()
4317 … csi_tmp &= ~( BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12 | BIT_13 | BIT_14 | BIT_15 ); in rtl8168_init_pci_offset_99()
4318 csi_tmp |= ( BIT_9 | BIT_10 | BIT_13 | BIT_14 | BIT_15 ); in rtl8168_init_pci_offset_99()
5125 rtl8168_clear_eth_phy_bit(tp, 0x14, BIT_9); in rtl8168_set_speed_xmii()
6057 rtl8168_set_eth_phy_bit(tp, 0x11, BIT_9); in rtl8168_enable_EEE()
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H A Dr8168.h1399 BIT_9 = (1 << 9), enumerator
/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dqla1280.h26 #define BIT_9 0x200 macro
138 #define ISP_FLASH_UPPER BIT_9 /* Flash upper bank select */
314 #define TP_STOP_QUEUE BIT_9 /* Stop que on check condition */
580 #define SF_GOT_TARGET BIT_9 /* */
/OK3568_Linux_fs/kernel/drivers/scsi/qla2xxx/
H A Dqla_def.h90 #define BIT_9 0x200 macro
1131 #define FO1_AE_AUTO_BYPASS BIT_9
1298 #define MBX_9 BIT_9
1967 #define PO_DIS_FRAME_MODE BIT_9
2072 #define SS_SENSE_LEN_VALID BIT_9
2478 #define NVME_PRLI_SP_PI_CTRL BIT_9
3321 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3787 #define RDP_PORT_SPEED_32GB BIT_9
4047 #define DT_ISP5422 BIT_9
H A Dqla_target.h92 #define OF_FAST_POST BIT_9 /* Enable mailbox fast posting. */
838 TRC_SRR_CTIO = BIT_9,
H A Dqla_fw.h534 #define TMF_ABORT_TASK_SET BIT_9
896 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */
1150 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
H A Dqla_sup.c2753 if (risc_attr & BIT_9) { in qla28xx_write_flash_data()
H A Dqla_target.c6874 nv->firmware_options_1 &= cpu_to_le32(~BIT_9); in qlt_24xx_config_nvram_stage1()
6979 nv->firmware_options_1 &= cpu_to_le32(~BIT_9); in qlt_81xx_config_nvram_stage1()
H A Dqla_os.c564 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; in qla2x00_pci_info_str()
636 if (ha->fw_attributes & BIT_9) { in qla2x00_fw_version_str()
H A Dqla_init.c7960 templates = (risc_attr & BIT_9) ? 2 : 1; in qla24xx_load_risc_flash()
8218 templates = (risc_attr & BIT_9) ? 2 : 1; in qla24xx_load_risc_blob()
/OK3568_Linux_fs/kernel/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hdr.h204 #define BIT_9 0x200 macro
H A Dqlcnic.h915 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
925 #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_9
H A Dqlcnic_hw.c819 #define QLCNIC_ENABLE_IPV6_LRO (BIT_1 | BIT_9)
H A Dqlcnic_sriov_common.c396 if (status & BIT_9) in qlcnic_sriov_get_vf_vport_info()
H A Dqlcnic_83xx_hw.c62 #define QLC_83XX_100_CAPABLE BIT_9
/OK3568_Linux_fs/kernel/drivers/scsi/qla4xxx/
H A Dql4_def.h90 #define BIT_9 0x200 macro
H A Dql4_os.c3666 SET_BITVAL(sess->dataseq_inorder_en, options, BIT_9); in qla4xxx_copy_to_fwddb_param()