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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/
H A Dallwinner,sun8i-r40-tcon-top.yaml27 / \ [2] TCON-TV0 [0] - TVE0/RGB
55 - description: The TCON TOP TVE0 clock
66 - const: tve0
275 "tve0",
H A Dsimple-framebuffer.yaml100 - de_be0-lcd0-tve0
105 - de_fe0-de_be0-lcd0-tve0
H A Dallwinner,sun4i-a10-tv-encoder.yaml45 tve0: tv-encoder@1c0a000 {
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun5i-r8.dtsi53 allwinner,pipeline = "de_be0-lcd0-tve0";
62 tve0: tv-encoder@01c0a000 { label
H A Dsun5i-r8-chip.dts236 &tve0 {
H A Dsun5i-a10s.dtsi85 allwinner,pipeline = "de_be0-lcd0-tve0";
H A Dsun5i-gr8.dtsi576 tve0: tv-encoder@01c0a000 { label
H A Dsun4i-a10.dtsi98 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
H A Dsun7i-a20.dtsi89 allwinner,pipeline = "de_be0-lcd0-tve0";
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dtve.h72 * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed
73 * dac from tve1. When using tve1 the mux value must be written to both tve0's
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dsun5i.dtsi80 framebuffer-lcd0-tve0 {
83 allwinner,pipeline = "de_be0-lcd0-tve0";
244 tve0: tv-encoder@1c0a000 { label
H A Dsun5i-r8-chip.dts243 &tve0 {
H A Dsun5i-gr8-evb.dts297 &tve0 {
H A Dsun4i-a10.dtsi96 framebuffer-fe0-lcd0-tve0 {
99 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
H A Dsun7i-a20.dtsi87 framebuffer-lcd0-tve0 {
90 allwinner,pipeline = "de_be0-lcd0-tve0";
H A Dsun8i-r40.dtsi890 "tve0",
/OK3568_Linux_fs/u-boot/drivers/video/sunxi/
H A Dsunxi_display.c1367 pipeline = PIPELINE_PREFIX "de_be0-lcd0-tve0";
1376 pipeline = PIPELINE_PREFIX "de_be0-lcd0-tve0";
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu-sun4i-a10.c354 static SUNXI_CCU_GATE(ahb_tve0_clk, "ahb-tve0", "ahb",
663 static SUNXI_CCU_GATE(dram_tve0_clk, "dram-tve0", "pll-ddr",
H A Dccu-sun8i-r40.c378 static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb1",
737 static SUNXI_CCU_M_WITH_MUX_GATE(tve0_clk, "tve0", tcon_parents,