1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner R40 TCON TOP Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun TCON TOPs main purpose is to configure whole display pipeline. It 15*4882a593Smuzhiyun determines relationships between mixers and TCONs, selects source 16*4882a593Smuzhiyun TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV 17*4882a593Smuzhiyun encoder clock source and contains additional TV TCON and DSI gates. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun It allows display pipeline to be configured in very different ways: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun / LCD0/LVDS0 22*4882a593Smuzhiyun / [0] TCON-LCD0 23*4882a593Smuzhiyun | \ MIPI DSI 24*4882a593Smuzhiyun mixer0 | 25*4882a593Smuzhiyun \ / [1] TCON-LCD1 - LCD1/LVDS1 26*4882a593Smuzhiyun TCON-TOP 27*4882a593Smuzhiyun / \ [2] TCON-TV0 [0] - TVE0/RGB 28*4882a593Smuzhiyun mixer1 | \ 29*4882a593Smuzhiyun | TCON-TOP - HDMI 30*4882a593Smuzhiyun | / 31*4882a593Smuzhiyun \ [3] TCON-TV1 [1] - TVE1/RGB 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun Note that both TCON TOP references same physical unit. Both mixers 34*4882a593Smuzhiyun can be connected to any TCON. Not all TCON TOP variants support all 35*4882a593Smuzhiyun features. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunproperties: 38*4882a593Smuzhiyun "#clock-cells": 39*4882a593Smuzhiyun const: 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun compatible: 42*4882a593Smuzhiyun enum: 43*4882a593Smuzhiyun - allwinner,sun8i-r40-tcon-top 44*4882a593Smuzhiyun - allwinner,sun50i-h6-tcon-top 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun reg: 47*4882a593Smuzhiyun maxItems: 1 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun clocks: 50*4882a593Smuzhiyun minItems: 2 51*4882a593Smuzhiyun maxItems: 6 52*4882a593Smuzhiyun items: 53*4882a593Smuzhiyun - description: The TCON TOP interface clock 54*4882a593Smuzhiyun - description: The TCON TOP TV0 clock 55*4882a593Smuzhiyun - description: The TCON TOP TVE0 clock 56*4882a593Smuzhiyun - description: The TCON TOP TV1 clock 57*4882a593Smuzhiyun - description: The TCON TOP TVE1 clock 58*4882a593Smuzhiyun - description: The TCON TOP MIPI DSI clock 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun clock-names: 61*4882a593Smuzhiyun minItems: 2 62*4882a593Smuzhiyun maxItems: 6 63*4882a593Smuzhiyun items: 64*4882a593Smuzhiyun - const: bus 65*4882a593Smuzhiyun - const: tcon-tv0 66*4882a593Smuzhiyun - const: tve0 67*4882a593Smuzhiyun - const: tcon-tv1 68*4882a593Smuzhiyun - const: tve1 69*4882a593Smuzhiyun - const: dsi 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun clock-output-names: 72*4882a593Smuzhiyun minItems: 1 73*4882a593Smuzhiyun maxItems: 3 74*4882a593Smuzhiyun description: > 75*4882a593Smuzhiyun The first item is the name of the clock created for the TV0 76*4882a593Smuzhiyun channel, the second item is the name of the TCON TV1 channel 77*4882a593Smuzhiyun clock and the third one is the name of the DSI channel clock. 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun resets: 80*4882a593Smuzhiyun maxItems: 1 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun ports: 83*4882a593Smuzhiyun type: object 84*4882a593Smuzhiyun description: | 85*4882a593Smuzhiyun A ports node with endpoint definitions as defined in 86*4882a593Smuzhiyun Documentation/devicetree/bindings/media/video-interfaces.txt. 87*4882a593Smuzhiyun All ports should have only one endpoint connected to 88*4882a593Smuzhiyun remote endpoint. 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun properties: 91*4882a593Smuzhiyun "#address-cells": 92*4882a593Smuzhiyun const: 1 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun "#size-cells": 95*4882a593Smuzhiyun const: 0 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun port@0: 98*4882a593Smuzhiyun type: object 99*4882a593Smuzhiyun description: | 100*4882a593Smuzhiyun Input endpoint for Mixer 0 mux. 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun port@1: 103*4882a593Smuzhiyun type: object 104*4882a593Smuzhiyun description: | 105*4882a593Smuzhiyun Output endpoint for Mixer 0 mux 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun properties: 108*4882a593Smuzhiyun "#address-cells": 109*4882a593Smuzhiyun const: 1 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun "#size-cells": 112*4882a593Smuzhiyun const: 0 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun reg: true 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun patternProperties: 117*4882a593Smuzhiyun "^endpoint@[0-9]$": 118*4882a593Smuzhiyun type: object 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun properties: 121*4882a593Smuzhiyun reg: 122*4882a593Smuzhiyun description: | 123*4882a593Smuzhiyun ID of the target TCON 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun required: 126*4882a593Smuzhiyun - reg 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun required: 129*4882a593Smuzhiyun - "#address-cells" 130*4882a593Smuzhiyun - "#size-cells" 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun additionalProperties: false 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun port@2: 135*4882a593Smuzhiyun type: object 136*4882a593Smuzhiyun description: | 137*4882a593Smuzhiyun Input endpoint for Mixer 1 mux. 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun port@3: 140*4882a593Smuzhiyun type: object 141*4882a593Smuzhiyun description: | 142*4882a593Smuzhiyun Output endpoint for Mixer 1 mux 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun properties: 145*4882a593Smuzhiyun "#address-cells": 146*4882a593Smuzhiyun const: 1 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun "#size-cells": 149*4882a593Smuzhiyun const: 0 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun reg: true 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun patternProperties: 154*4882a593Smuzhiyun "^endpoint@[0-9]$": 155*4882a593Smuzhiyun type: object 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun properties: 158*4882a593Smuzhiyun reg: 159*4882a593Smuzhiyun description: | 160*4882a593Smuzhiyun ID of the target TCON 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun required: 163*4882a593Smuzhiyun - reg 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun required: 166*4882a593Smuzhiyun - "#address-cells" 167*4882a593Smuzhiyun - "#size-cells" 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun additionalProperties: false 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun port@4: 172*4882a593Smuzhiyun type: object 173*4882a593Smuzhiyun description: | 174*4882a593Smuzhiyun Input endpoint for HDMI mux. 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun properties: 177*4882a593Smuzhiyun "#address-cells": 178*4882a593Smuzhiyun const: 1 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun "#size-cells": 181*4882a593Smuzhiyun const: 0 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun reg: true 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun patternProperties: 186*4882a593Smuzhiyun "^endpoint@[0-9]$": 187*4882a593Smuzhiyun type: object 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun properties: 190*4882a593Smuzhiyun reg: 191*4882a593Smuzhiyun description: | 192*4882a593Smuzhiyun ID of the target TCON 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun required: 195*4882a593Smuzhiyun - reg 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun required: 198*4882a593Smuzhiyun - "#address-cells" 199*4882a593Smuzhiyun - "#size-cells" 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun additionalProperties: false 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun port@5: 204*4882a593Smuzhiyun type: object 205*4882a593Smuzhiyun description: | 206*4882a593Smuzhiyun Output endpoint for HDMI mux 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun required: 209*4882a593Smuzhiyun - "#address-cells" 210*4882a593Smuzhiyun - "#size-cells" 211*4882a593Smuzhiyun - port@0 212*4882a593Smuzhiyun - port@1 213*4882a593Smuzhiyun - port@4 214*4882a593Smuzhiyun - port@5 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun additionalProperties: false 217*4882a593Smuzhiyun 218*4882a593Smuzhiyunrequired: 219*4882a593Smuzhiyun - "#clock-cells" 220*4882a593Smuzhiyun - compatible 221*4882a593Smuzhiyun - reg 222*4882a593Smuzhiyun - clocks 223*4882a593Smuzhiyun - clock-names 224*4882a593Smuzhiyun - clock-output-names 225*4882a593Smuzhiyun - resets 226*4882a593Smuzhiyun - ports 227*4882a593Smuzhiyun 228*4882a593SmuzhiyunadditionalProperties: false 229*4882a593Smuzhiyun 230*4882a593Smuzhiyunif: 231*4882a593Smuzhiyun properties: 232*4882a593Smuzhiyun compatible: 233*4882a593Smuzhiyun contains: 234*4882a593Smuzhiyun const: allwinner,sun50i-h6-tcon-top 235*4882a593Smuzhiyun 236*4882a593Smuzhiyunthen: 237*4882a593Smuzhiyun properties: 238*4882a593Smuzhiyun clocks: 239*4882a593Smuzhiyun maxItems: 2 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun clock-output-names: 242*4882a593Smuzhiyun maxItems: 1 243*4882a593Smuzhiyun 244*4882a593Smuzhiyunelse: 245*4882a593Smuzhiyun properties: 246*4882a593Smuzhiyun clocks: 247*4882a593Smuzhiyun minItems: 6 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun clock-output-names: 250*4882a593Smuzhiyun minItems: 3 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun ports: 253*4882a593Smuzhiyun required: 254*4882a593Smuzhiyun - port@2 255*4882a593Smuzhiyun - port@3 256*4882a593Smuzhiyun 257*4882a593Smuzhiyunexamples: 258*4882a593Smuzhiyun - | 259*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun #include <dt-bindings/clock/sun8i-r40-ccu.h> 262*4882a593Smuzhiyun #include <dt-bindings/reset/sun8i-r40-ccu.h> 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun tcon_top: tcon-top@1c70000 { 265*4882a593Smuzhiyun compatible = "allwinner,sun8i-r40-tcon-top"; 266*4882a593Smuzhiyun reg = <0x01c70000 0x1000>; 267*4882a593Smuzhiyun clocks = <&ccu CLK_BUS_TCON_TOP>, 268*4882a593Smuzhiyun <&ccu CLK_TCON_TV0>, 269*4882a593Smuzhiyun <&ccu CLK_TVE0>, 270*4882a593Smuzhiyun <&ccu CLK_TCON_TV1>, 271*4882a593Smuzhiyun <&ccu CLK_TVE1>, 272*4882a593Smuzhiyun <&ccu CLK_DSI_DPHY>; 273*4882a593Smuzhiyun clock-names = "bus", 274*4882a593Smuzhiyun "tcon-tv0", 275*4882a593Smuzhiyun "tve0", 276*4882a593Smuzhiyun "tcon-tv1", 277*4882a593Smuzhiyun "tve1", 278*4882a593Smuzhiyun "dsi"; 279*4882a593Smuzhiyun clock-output-names = "tcon-top-tv0", 280*4882a593Smuzhiyun "tcon-top-tv1", 281*4882a593Smuzhiyun "tcon-top-dsi"; 282*4882a593Smuzhiyun resets = <&ccu RST_BUS_TCON_TOP>; 283*4882a593Smuzhiyun #clock-cells = <1>; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun ports { 286*4882a593Smuzhiyun #address-cells = <1>; 287*4882a593Smuzhiyun #size-cells = <0>; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun tcon_top_mixer0_in: port@0 { 290*4882a593Smuzhiyun reg = <0>; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun tcon_top_mixer0_in_mixer0: endpoint { 293*4882a593Smuzhiyun remote-endpoint = <&mixer0_out_tcon_top>; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun }; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun tcon_top_mixer0_out: port@1 { 298*4882a593Smuzhiyun #address-cells = <1>; 299*4882a593Smuzhiyun #size-cells = <0>; 300*4882a593Smuzhiyun reg = <1>; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 303*4882a593Smuzhiyun reg = <0>; 304*4882a593Smuzhiyun }; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { 307*4882a593Smuzhiyun reg = <1>; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 311*4882a593Smuzhiyun reg = <2>; 312*4882a593Smuzhiyun remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 313*4882a593Smuzhiyun }; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun tcon_top_mixer0_out_tcon_tv1: endpoint@3 { 316*4882a593Smuzhiyun reg = <3>; 317*4882a593Smuzhiyun remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun tcon_top_mixer1_in: port@2 { 322*4882a593Smuzhiyun #address-cells = <1>; 323*4882a593Smuzhiyun #size-cells = <0>; 324*4882a593Smuzhiyun reg = <2>; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun tcon_top_mixer1_in_mixer1: endpoint@1 { 327*4882a593Smuzhiyun reg = <1>; 328*4882a593Smuzhiyun remote-endpoint = <&mixer1_out_tcon_top>; 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun tcon_top_mixer1_out: port@3 { 333*4882a593Smuzhiyun #address-cells = <1>; 334*4882a593Smuzhiyun #size-cells = <0>; 335*4882a593Smuzhiyun reg = <3>; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 338*4882a593Smuzhiyun reg = <0>; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { 342*4882a593Smuzhiyun reg = <1>; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 346*4882a593Smuzhiyun reg = <2>; 347*4882a593Smuzhiyun remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 348*4882a593Smuzhiyun }; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun tcon_top_mixer1_out_tcon_tv1: endpoint@3 { 351*4882a593Smuzhiyun reg = <3>; 352*4882a593Smuzhiyun remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun }; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun tcon_top_hdmi_in: port@4 { 357*4882a593Smuzhiyun #address-cells = <1>; 358*4882a593Smuzhiyun #size-cells = <0>; 359*4882a593Smuzhiyun reg = <4>; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun tcon_top_hdmi_in_tcon_tv0: endpoint@0 { 362*4882a593Smuzhiyun reg = <0>; 363*4882a593Smuzhiyun remote-endpoint = <&tcon_tv0_out_tcon_top>; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun tcon_top_hdmi_in_tcon_tv1: endpoint@1 { 367*4882a593Smuzhiyun reg = <1>; 368*4882a593Smuzhiyun remote-endpoint = <&tcon_tv1_out_tcon_top>; 369*4882a593Smuzhiyun }; 370*4882a593Smuzhiyun }; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun tcon_top_hdmi_out: port@5 { 373*4882a593Smuzhiyun reg = <5>; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun tcon_top_hdmi_out_hdmi: endpoint { 376*4882a593Smuzhiyun remote-endpoint = <&hdmi_in_tcon_top>; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun }; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun... 383