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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Dvideo-interfaces.txt4 ---------------
21 #address-cells = <1>;
22 #size-cells = <0>;
37 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
41 specify #address-cells, #size-cells properties independently for the 'port'
44 Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
53 a device is partitioned into multiple data busses, e.g. 16-bit input port
54 divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
55 and data-shift properties can be used to assign physical data lines to each
59 --------------------------------
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dsimple-card.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
16 $ref: /schemas/types.yaml#/definitions/phandle-array
19 bitclock-master:
20 description: Indicates dai-link bit clock master
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/OK3568_Linux_fs/kernel/sound/soc/ti/
H A Domap3pandora.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap3pandora.c -- SoC audio for Pandora Handheld Console
19 #include <asm/mach-types.h>
20 #include <linux/platform_data/asoc-ti-mcbsp.h>
22 #include "omap-mcbsp.h"
39 /* Set the codec system clock for DAC and ADC */ in omap3pandora_hw_params()
43 pr_err(PREFIX "can't set codec system clock\n"); in omap3pandora_hw_params()
47 /* Set McBSP clock to external */ in omap3pandora_hw_params()
52 pr_err(PREFIX "can't set cpu system clock\n"); in omap3pandora_hw_params()
58 pr_err(PREFIX "can't set SRG clock divider\n"); in omap3pandora_hw_params()
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/OK3568_Linux_fs/kernel/sound/soc/atmel/
H A Datmel_ssc_dai.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * atmel_ssc_dai.h - ALSA SSC interface for the Atmel SoC
11 * Based on at91-ssc.c by
21 #include <linux/atmel-ssc.h>
23 #include "atmel-pcm.h"
25 /* SSC system clock ids */
26 #define ATMEL_SYSCLK_MCK 0 /* SSC uses AT91 MCK as system clock */
33 * SSC direction masks
40 * SSC register values that Atmel left out of <linux/atmel-ssc.h>. These
/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A DMC68328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
31 * System Control Register (SCR)
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
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H A DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
32 * System Control Register (SCR)
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
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H A DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
34 * System Control Register (SCR)
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
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/OK3568_Linux_fs/kernel/Documentation/driver-api/gpio/
H A Dlegacy.rst13 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
21 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
22 non-dedicated pin can be configured as a GPIO; and most chips have at least
27 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
32 - Output values are writable (high=1, low=0). Some chips also have
34 value might be driven ... supporting "wire-OR" and similar schemes
37 - Input values are likewise readable (1, 0). Some chips support readback
38 of pins configured as "output", which is very useful in such "wire-OR"
40 input de-glitch/debounce logic, sometimes with software controls.
42 - Inputs can often be used as IRQ signals, often edge triggered but
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/OK3568_Linux_fs/kernel/Documentation/spi/
H A Dspi-summary.rst5 02-Feb-2012
8 ------------
14 The three signal wires hold a clock (SCK, often on the order of 10 MHz),
15 and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
16 Slave Out" (MISO) signals. (Other names are also used.) There are four
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
18 commonly used. Each clock cycle shifts data out and data in; the clock
32 - SPI may be used for request/response style device protocols, as with
35 - It may also be used to stream data in either direction (half duplex),
38 - Some devices may use eight bit words. Others may use different word
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/OK3568_Linux_fs/kernel/Documentation/scsi/
H A DChangeLog.sym53c8xx1 Sat May 12 12:00 2001 Gerard Roudier (groudier@club-internet.fr)
2 * version sym53c8xx-1.7.3c
3 - Ensure LEDC bit in GPCNTL is cleared when reading the NVRAM.
4 Fix sent by Stig Telfer <stig@api-networks.com>.
5 - Backport from SYM-2 the work-around that allows to support
7 - Check that we received at least 8 bytes of INQUIRY response
9 - Define scsi_set_pci_device() as nil for kernel < 2.4.4.
10 - + A couple of minor changes.
12 Sat Apr 7 19:30 2001 Gerard Roudier (groudier@club-internet.fr)
13 * version sym53c8xx-1.7.3b
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/OK3568_Linux_fs/kernel/sound/soc/fsl/
H A Dfsl_esai.c1 // SPDX-License-Identifier: GPL-2.0
17 #include "imx-pcm.h"
25 * struct fsl_esai_soc_data - soc specific data
35 * struct fsl_esai - ESAI private data
40 * @coreclk: clock source to access register
41 * @extalclk: esai clock source to derive HCK, SCK and FS
42 * @fsysclk: system clock source to derive HCK, SCK and FS
43 * @spbaclk: SPBA clock (optional, depending on SoC design)
53 * @hck_rate: clock rate of desired HCKx clock
54 * @sck_rate: clock rate of desired SCKx clock
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/OK3568_Linux_fs/kernel/drivers/media/usb/dvb-usb-v2/
H A Drtl28xxu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
138 * 0x3000 SYS : system
146 #define USB_SYSCTL 0x2000 /* USB system control */
147 #define USB_SYSCTL_0 0x2000 /* USB system control */
148 #define USB_SYSCTL_1 0x2001 /* USB system control */
149 #define USB_SYSCTL_2 0x2002 /* USB system control */
150 #define USB_SYSCTL_3 0x2003 /* USB system control */
196 #define USB_TOUT_VAL 0x2F08 /* USB time-out time */
200 #define USB_VSTAOUT 0x2F1C /* UTMI vendor signal status out */
209 #define USB_SLBBIST 0x2FA0 /* self-loop-back BIST */
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/OK3568_Linux_fs/kernel/sound/pci/ice1712/
H A Denvy24ht.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 #define ICEREG1724(ice, x) ((ice)->port + VT1724_REG_##x)
49 #define VT1724_REG_SYS_CFG 0x04 /* byte - system configuration PCI60 on Envy24*/
60 #define VT1724_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */
65 #define VT1724_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */
96 #define VT1724_I2C_WRITE 0x01 /* write direction */
106 bit3 - during reset used for Eeprom power-on strapping
109 #define VT1724_REG_GPIO_DATA_22 0x1e /* byte direction for GPIO 16:22 */
114 * Professional multi-track direct control registers
117 #define ICEMT1724(ice, x) ((ice)->profi_port + VT1724_MT_##x)
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H A Dquartet.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 unsigned int scr; /* system control register */
51 static const char * const ext_clock_names[3] = {"IEC958 In", "Word Clock 1xFS",
52 "Word Clock 256xFS"};
65 /* GPIO0 - O - DATA0, def. 0 */
67 /* GPIO1 - I/O - DATA1, Jack Detect Input0 (0:present, 1:missing), def. 1 */
69 /* GPIO2 - I/O - DATA2, Jack Detect Input1 (0:present, 1:missing), def. 1 */
71 /* GPIO3 - I/O - DATA3, def. 1 */
73 /* GPIO4 - I/O - DATA4, SPI CDTO, def. 1 */
75 /* GPIO5 - I/O - DATA5, SPI CCLK, def. 1 */
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/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/include/mach/
H A Dmipi_dsim.h7 * SPDX-License-Identifier: GPL-2.0+
63 /* MIPI DSI Processor-to-Peripheral transaction types */
112 * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
140 * in Non-burst mode, RGB data area is filled with RGB data and NULL
144 * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8)
147 * clock(System clock cycle base)
148 * if the timer value goes to 0x00000000, the clock stable bit of status
150 * @esc_clk: specifies escape clock frequency for getting the escape clock
155 * BTA requests to D-PHY automatically. this counter value specifies
158 * this register specifies time out from BTA request to change
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/OK3568_Linux_fs/kernel/drivers/soundwire/
H A Dintel.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-17 Intel Corporation.
31 * flags reused in each byte, with master0 using the ls-byte, etc.
70 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
71 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
158 timeout--; in intel_wait_bit()
162 return -EAGAIN; in intel_wait_bit()
194 return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value); in intel_sprintf()
199 struct sdw_intel *sdw = s_file->private; in intel_reg_show()
200 void __iomem *s = sdw->link_res->shim; in intel_reg_show()
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/OK3568_Linux_fs/kernel/arch/arm/mm/
H A Dproc-xscale.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-xscale.S
25 #include <asm/pgtable-hwdef.h>
28 #include "proc-macros.S"
59 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
65 * when we have to ensure that the last operation to the co-pro
134 * Perform a soft reset of the system. Put the CPU into the
147 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
148 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
172 * XScale supports clock switching, but using idle mode support
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H A Dproc-xsc3.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-xsc3.S
15 * - ARMv6 Supersections
16 * - Low Locality Reference pages (replaces mini-cache)
17 * - 36-bit addressing
18 * - L2 cache
19 * - Cache coherency if chipset supports it
29 #include <asm/pgtable-hwdef.h>
32 #include "proc-macros.S"
98 * Perform a soft reset of the system. Put the CPU into the
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/OK3568_Linux_fs/kernel/include/linux/usb/
H A Dr8a66597.h1 // SPDX-License-Identifier: GPL-2.0
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
137 /* System Configuration Control Register */
138 #define XTAL 0xC000 /* b15-14: Crystal selection */
142 #define XCKE 0x2000 /* b13: External clock enable */
144 #define SCKE 0x0400 /* b10: USB clock enable */
147 #define HSE 0x0080 /* b7: Hi-speed enable */
149 #define DRPD 0x0020 /* b5: D+/- pull down control */
153 /* System Configuration Status Register */
154 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
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/OK3568_Linux_fs/kernel/drivers/macintosh/
H A Dvia-cuda.c1 // SPDX-License-Identifier: GPL-2.0
3 * Device driver for the Cuda and Egret system controllers found on PowerMacs
7 * This MCU controls system power, Parameter RAM, Real Time Clock and the
35 /* VIA registers - spaced 0x200 bytes apart */
37 #define B 0 /* B-side data */
38 #define A RS /* A-side data */
39 #define DIRB (2*RS) /* B-side direction (1=output) */
40 #define DIRA (3*RS) /* A-side direction (1=output) */
52 #define ANH (15*RS) /* A-side data, no handshake */
59 * ----------------+------------------------------------------
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/OK3568_Linux_fs/kernel/include/linux/soundwire/
H A Dsdw.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
71 * enum sdw_slave_status - Slave status
85 * enum sdw_clk_stop_type: clock stop operations
87 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare
88 * @SDW_CLK_POST_PREPARE: post clock stop prepare
89 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
90 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
100 * enum sdw_command_response - Command response as defined by SDW spec
142 * enum sdw_data_direction: Data direction
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/OK3568_Linux_fs/u-boot/drivers/sound/
H A Dwm8994.c5 * SPDX-License-Identifier: GPL-2.0+
21 /* defines for wm8994 system clock selection */
31 int out; /* output frequency in Hz */ member
38 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
39 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
40 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
50 /* op clock divisions */
53 /* lr clock frame size ratio */
58 /* bit clock divisors */
103 * @return int value 0 for success, -1 in case of error.
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/OK3568_Linux_fs/kernel/Documentation/staging/
H A Dstatic-keys.rst30 performance-sensitive fast-path kernel code, via a GCC feature and a code
74 https://gcc.gnu.org/ml/gcc-patches/2009-07/msg01556.html
77 by default, without the need to check memory. Then, at run-time, we can patch
78 the branch site to change the branch direction.
86 consist of a single atomic 'no-op' instruction (5 bytes on x86), in the
87 straight-line code path. When the branch is 'flipped', we will patch the
88 'no-op' in the straight-line codepath with a 'jump' instruction to the
89 out-of-line true branch. Thus, changing branch direction is expensive but
110 allocated at run-time.
186 struct jump_entry table must be at least 4-byte aligned because the
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/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Dfsl_esdhc.c2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
25 #include <asm-generic/gpio.h>
37 uint dsaddr; /* SDMA system address register */
48 uint sysctl; /* System Control Register */
59 uint adsaddr; /* ADMA system address register */
79 uint sddirctl; /* SD direction control register */
99 * @non_removable: 0: removable; 1: non-removable
132 if (data->blocks > 1) { in esdhc_xfertyp()
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/OK3568_Linux_fs/kernel/Documentation/networking/dsa/
H A Dsja1105.rst10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
17 These are SPI-managed automotive switches, with all ports being gigabit
21 set-and-forget use, with minimal dynamic interaction at runtime. They
47 Clock Sync Params no no
56 Also the configuration is write-only (software cannot read it back from the
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