1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * atmel_ssc_dai.h - ALSA SSC interface for the Atmel SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2005 SAN People 6*4882a593Smuzhiyun * Copyright (C) 2008 Atmel 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com> 9*4882a593Smuzhiyun * ATMEL CORP. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Based on at91-ssc.c by 12*4882a593Smuzhiyun * Frank Mandarino <fmandarino@endrelia.com> 13*4882a593Smuzhiyun * Based on pxa2xx Platform drivers by 14*4882a593Smuzhiyun * Liam Girdwood <lrg@slimlogic.co.uk> 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef _ATMEL_SSC_DAI_H 18*4882a593Smuzhiyun #define _ATMEL_SSC_DAI_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <linux/types.h> 21*4882a593Smuzhiyun #include <linux/atmel-ssc.h> 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #include "atmel-pcm.h" 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* SSC system clock ids */ 26*4882a593Smuzhiyun #define ATMEL_SYSCLK_MCK 0 /* SSC uses AT91 MCK as system clock */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* SSC divider ids */ 29*4882a593Smuzhiyun #define ATMEL_SSC_CMR_DIV 0 /* MCK divider for BCLK */ 30*4882a593Smuzhiyun #define ATMEL_SSC_TCMR_PERIOD 1 /* BCLK divider for transmit FS */ 31*4882a593Smuzhiyun #define ATMEL_SSC_RCMR_PERIOD 2 /* BCLK divider for receive FS */ 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * SSC direction masks 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun #define SSC_DIR_MASK_UNUSED 0 36*4882a593Smuzhiyun #define SSC_DIR_MASK_PLAYBACK 1 37*4882a593Smuzhiyun #define SSC_DIR_MASK_CAPTURE 2 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * SSC register values that Atmel left out of <linux/atmel-ssc.h>. These 41*4882a593Smuzhiyun * are expected to be used with SSC_BF 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun /* START bit field values */ 44*4882a593Smuzhiyun #define SSC_START_CONTINUOUS 0 45*4882a593Smuzhiyun #define SSC_START_TX_RX 1 46*4882a593Smuzhiyun #define SSC_START_LOW_RF 2 47*4882a593Smuzhiyun #define SSC_START_HIGH_RF 3 48*4882a593Smuzhiyun #define SSC_START_FALLING_RF 4 49*4882a593Smuzhiyun #define SSC_START_RISING_RF 5 50*4882a593Smuzhiyun #define SSC_START_LEVEL_RF 6 51*4882a593Smuzhiyun #define SSC_START_EDGE_RF 7 52*4882a593Smuzhiyun #define SSS_START_COMPARE_0 8 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* CKI bit field values */ 55*4882a593Smuzhiyun #define SSC_CKI_FALLING 0 56*4882a593Smuzhiyun #define SSC_CKI_RISING 1 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* CKO bit field values */ 59*4882a593Smuzhiyun #define SSC_CKO_NONE 0 60*4882a593Smuzhiyun #define SSC_CKO_CONTINUOUS 1 61*4882a593Smuzhiyun #define SSC_CKO_TRANSFER 2 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* CKS bit field values */ 64*4882a593Smuzhiyun #define SSC_CKS_DIV 0 65*4882a593Smuzhiyun #define SSC_CKS_CLOCK 1 66*4882a593Smuzhiyun #define SSC_CKS_PIN 2 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* FSEDGE bit field values */ 69*4882a593Smuzhiyun #define SSC_FSEDGE_POSITIVE 0 70*4882a593Smuzhiyun #define SSC_FSEDGE_NEGATIVE 1 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* FSOS bit field values */ 73*4882a593Smuzhiyun #define SSC_FSOS_NONE 0 74*4882a593Smuzhiyun #define SSC_FSOS_NEGATIVE 1 75*4882a593Smuzhiyun #define SSC_FSOS_POSITIVE 2 76*4882a593Smuzhiyun #define SSC_FSOS_LOW 3 77*4882a593Smuzhiyun #define SSC_FSOS_HIGH 4 78*4882a593Smuzhiyun #define SSC_FSOS_TOGGLE 5 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define START_DELAY 1 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct atmel_ssc_state { 83*4882a593Smuzhiyun u32 ssc_cmr; 84*4882a593Smuzhiyun u32 ssc_rcmr; 85*4882a593Smuzhiyun u32 ssc_rfmr; 86*4882a593Smuzhiyun u32 ssc_tcmr; 87*4882a593Smuzhiyun u32 ssc_tfmr; 88*4882a593Smuzhiyun u32 ssc_sr; 89*4882a593Smuzhiyun u32 ssc_imr; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct atmel_ssc_info { 94*4882a593Smuzhiyun char *name; 95*4882a593Smuzhiyun struct ssc_device *ssc; 96*4882a593Smuzhiyun unsigned short dir_mask; /* 0=unused, 1=playback, 2=capture */ 97*4882a593Smuzhiyun unsigned short initialized; /* true if SSC has been initialized */ 98*4882a593Smuzhiyun unsigned short daifmt; 99*4882a593Smuzhiyun unsigned short cmr_div; 100*4882a593Smuzhiyun unsigned short tcmr_period; 101*4882a593Smuzhiyun unsigned short rcmr_period; 102*4882a593Smuzhiyun unsigned int forced_divider; 103*4882a593Smuzhiyun struct atmel_pcm_dma_params *dma_params[2]; 104*4882a593Smuzhiyun struct atmel_ssc_state ssc_state; 105*4882a593Smuzhiyun unsigned long mck_rate; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun int atmel_ssc_set_audio(int ssc_id); 109*4882a593Smuzhiyun void atmel_ssc_put_audio(int ssc_id); 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #endif /* _AT91_SSC_DAI_H */ 112