1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2012 Samsung Electronics
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Author: InKi Dae <inki.dae@samsung.com>
5*4882a593Smuzhiyun * Author: Donghwa Lee <dh09.lee@samsung.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #ifndef _DSIM_H
11*4882a593Smuzhiyun #define _DSIM_H
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/list.h>
14*4882a593Smuzhiyun #include <linux/fb.h>
15*4882a593Smuzhiyun #include <lcd.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define PANEL_NAME_SIZE (32)
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun enum mipi_dsim_interface_type {
20*4882a593Smuzhiyun DSIM_COMMAND,
21*4882a593Smuzhiyun DSIM_VIDEO
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun enum mipi_dsim_virtual_ch_no {
25*4882a593Smuzhiyun DSIM_VIRTUAL_CH_0,
26*4882a593Smuzhiyun DSIM_VIRTUAL_CH_1,
27*4882a593Smuzhiyun DSIM_VIRTUAL_CH_2,
28*4882a593Smuzhiyun DSIM_VIRTUAL_CH_3
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun enum mipi_dsim_burst_mode_type {
32*4882a593Smuzhiyun DSIM_NON_BURST_SYNC_EVENT,
33*4882a593Smuzhiyun DSIM_BURST_SYNC_EVENT,
34*4882a593Smuzhiyun DSIM_NON_BURST_SYNC_PULSE,
35*4882a593Smuzhiyun DSIM_BURST,
36*4882a593Smuzhiyun DSIM_NON_VIDEO_MODE
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun enum mipi_dsim_no_of_data_lane {
40*4882a593Smuzhiyun DSIM_DATA_LANE_1,
41*4882a593Smuzhiyun DSIM_DATA_LANE_2,
42*4882a593Smuzhiyun DSIM_DATA_LANE_3,
43*4882a593Smuzhiyun DSIM_DATA_LANE_4
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun enum mipi_dsim_byte_clk_src {
47*4882a593Smuzhiyun DSIM_PLL_OUT_DIV8,
48*4882a593Smuzhiyun DSIM_EXT_CLK_DIV8,
49*4882a593Smuzhiyun DSIM_EXT_CLK_BYPASS
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun enum mipi_dsim_pixel_format {
53*4882a593Smuzhiyun DSIM_CMD_3BPP,
54*4882a593Smuzhiyun DSIM_CMD_8BPP,
55*4882a593Smuzhiyun DSIM_CMD_12BPP,
56*4882a593Smuzhiyun DSIM_CMD_16BPP,
57*4882a593Smuzhiyun DSIM_VID_16BPP_565,
58*4882a593Smuzhiyun DSIM_VID_18BPP_666PACKED,
59*4882a593Smuzhiyun DSIM_18BPP_666LOOSELYPACKED,
60*4882a593Smuzhiyun DSIM_24BPP_888
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* MIPI DSI Processor-to-Peripheral transaction types */
64*4882a593Smuzhiyun enum {
65*4882a593Smuzhiyun MIPI_DSI_V_SYNC_START = 0x01,
66*4882a593Smuzhiyun MIPI_DSI_V_SYNC_END = 0x11,
67*4882a593Smuzhiyun MIPI_DSI_H_SYNC_START = 0x21,
68*4882a593Smuzhiyun MIPI_DSI_H_SYNC_END = 0x31,
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun MIPI_DSI_COLOR_MODE_OFF = 0x02,
71*4882a593Smuzhiyun MIPI_DSI_COLOR_MODE_ON = 0x12,
72*4882a593Smuzhiyun MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
73*4882a593Smuzhiyun MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
76*4882a593Smuzhiyun MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
77*4882a593Smuzhiyun MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
80*4882a593Smuzhiyun MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
81*4882a593Smuzhiyun MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun MIPI_DSI_DCS_SHORT_WRITE = 0x05,
84*4882a593Smuzhiyun MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun MIPI_DSI_DCS_READ = 0x06,
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun MIPI_DSI_END_OF_TRANSMISSION = 0x08,
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun MIPI_DSI_NULL_PACKET = 0x09,
93*4882a593Smuzhiyun MIPI_DSI_BLANKING_PACKET = 0x19,
94*4882a593Smuzhiyun MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
95*4882a593Smuzhiyun MIPI_DSI_DCS_LONG_WRITE = 0x39,
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
98*4882a593Smuzhiyun MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
99*4882a593Smuzhiyun MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
102*4882a593Smuzhiyun MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
103*4882a593Smuzhiyun MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
106*4882a593Smuzhiyun MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
107*4882a593Smuzhiyun MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
108*4882a593Smuzhiyun MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /*
112*4882a593Smuzhiyun * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
113*4882a593Smuzhiyun *
114*4882a593Smuzhiyun * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse.
115*4882a593Smuzhiyun * @eot_disable: enable or disable EoT packet in HS mode.
116*4882a593Smuzhiyun * @auto_vertical_cnt: specifies auto vertical count mode.
117*4882a593Smuzhiyun * in Video mode, the vertical line transition uses line counter
118*4882a593Smuzhiyun * configured by VSA, VBP, and Vertical resolution.
119*4882a593Smuzhiyun * If this bit is set to '1', the line counter does not use VSA and VBP
120*4882a593Smuzhiyun * registers.(in command mode, this variable is ignored)
121*4882a593Smuzhiyun * @hse: set horizontal sync event mode.
122*4882a593Smuzhiyun * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
123*4882a593Smuzhiyun * start packet to MIPI DSI slave at MIPI DSI spec1.1r02.
124*4882a593Smuzhiyun * this bit transfers HSYNC end packet in VSYNC pulse and Vporch area
125*4882a593Smuzhiyun * (in mommand mode, this variable is ignored)
126*4882a593Smuzhiyun * @hfp: specifies HFP disable mode.
127*4882a593Smuzhiyun * if this variable is set, DSI master ignores HFP area in VIDEO mode.
128*4882a593Smuzhiyun * (in command mode, this variable is ignored)
129*4882a593Smuzhiyun * @hbp: specifies HBP disable mode.
130*4882a593Smuzhiyun * if this variable is set, DSI master ignores HBP area in VIDEO mode.
131*4882a593Smuzhiyun * (in command mode, this variable is ignored)
132*4882a593Smuzhiyun * @hsa: specifies HSA disable mode.
133*4882a593Smuzhiyun * if this variable is set, DSI master ignores HSA area in VIDEO mode.
134*4882a593Smuzhiyun * (in command mode, this variable is ignored)
135*4882a593Smuzhiyun * @e_interface: specifies interface to be used.(CPU or RGB interface)
136*4882a593Smuzhiyun * @e_virtual_ch: specifies virtual channel number that main or
137*4882a593Smuzhiyun * sub diaplsy uses.
138*4882a593Smuzhiyun * @e_pixel_format: specifies pixel stream format for main or sub display.
139*4882a593Smuzhiyun * @e_burst_mode: selects Burst mode in Video mode.
140*4882a593Smuzhiyun * in Non-burst mode, RGB data area is filled with RGB data and NULL
141*4882a593Smuzhiyun * packets, according to input bandwidth of RGB interface.
142*4882a593Smuzhiyun * In Burst mode, RGB data area is filled with RGB data only.
143*4882a593Smuzhiyun * @e_no_data_lane: specifies data lane count to be used by Master.
144*4882a593Smuzhiyun * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8)
145*4882a593Smuzhiyun * DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
146*4882a593Smuzhiyun * @pll_stable_time: specifies the PLL Timer for stability of the ganerated
147*4882a593Smuzhiyun * clock(System clock cycle base)
148*4882a593Smuzhiyun * if the timer value goes to 0x00000000, the clock stable bit of status
149*4882a593Smuzhiyun * and interrupt register is set.
150*4882a593Smuzhiyun * @esc_clk: specifies escape clock frequency for getting the escape clock
151*4882a593Smuzhiyun * prescaler value.
152*4882a593Smuzhiyun * @stop_holding_cnt: specifies the interval value between transmitting
153*4882a593Smuzhiyun * read packet(or write "set_tear_on" command) and BTA request.
154*4882a593Smuzhiyun * after transmitting read packet or write "set_tear_on" command,
155*4882a593Smuzhiyun * BTA requests to D-PHY automatically. this counter value specifies
156*4882a593Smuzhiyun * the interval between them.
157*4882a593Smuzhiyun * @bta_timeout: specifies the timer for BTA.
158*4882a593Smuzhiyun * this register specifies time out from BTA request to change
159*4882a593Smuzhiyun * the direction with respect to Tx escape clock.
160*4882a593Smuzhiyun * @rx_timeout: specifies the timer for LP Rx mode timeout.
161*4882a593Smuzhiyun * this register specifies time out on how long RxValid deasserts,
162*4882a593Smuzhiyun * after RxLpdt asserts with respect to Tx escape clock.
163*4882a593Smuzhiyun * - RxValid specifies Rx data valid indicator.
164*4882a593Smuzhiyun * - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode.
165*4882a593Smuzhiyun * - RxValid and RxLpdt specifies signal from D-PHY.
166*4882a593Smuzhiyun */
167*4882a593Smuzhiyun struct mipi_dsim_config {
168*4882a593Smuzhiyun unsigned char auto_flush;
169*4882a593Smuzhiyun unsigned char eot_disable;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun unsigned char auto_vertical_cnt;
172*4882a593Smuzhiyun unsigned char hse;
173*4882a593Smuzhiyun unsigned char hfp;
174*4882a593Smuzhiyun unsigned char hbp;
175*4882a593Smuzhiyun unsigned char hsa;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun enum mipi_dsim_interface_type e_interface;
178*4882a593Smuzhiyun enum mipi_dsim_virtual_ch_no e_virtual_ch;
179*4882a593Smuzhiyun enum mipi_dsim_pixel_format e_pixel_format;
180*4882a593Smuzhiyun enum mipi_dsim_burst_mode_type e_burst_mode;
181*4882a593Smuzhiyun enum mipi_dsim_no_of_data_lane e_no_data_lane;
182*4882a593Smuzhiyun enum mipi_dsim_byte_clk_src e_byte_clk;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /*
185*4882a593Smuzhiyun * ===========================================
186*4882a593Smuzhiyun * | P | M | S | MHz |
187*4882a593Smuzhiyun * -------------------------------------------
188*4882a593Smuzhiyun * | 3 | 100 | 3 | 100 |
189*4882a593Smuzhiyun * | 3 | 100 | 2 | 200 |
190*4882a593Smuzhiyun * | 3 | 63 | 1 | 252 |
191*4882a593Smuzhiyun * | 4 | 100 | 1 | 300 |
192*4882a593Smuzhiyun * | 4 | 110 | 1 | 330 |
193*4882a593Smuzhiyun * | 12 | 350 | 1 | 350 |
194*4882a593Smuzhiyun * | 3 | 100 | 1 | 400 |
195*4882a593Smuzhiyun * | 4 | 150 | 1 | 450 |
196*4882a593Smuzhiyun * | 6 | 118 | 1 | 472 |
197*4882a593Smuzhiyun * | 3 | 120 | 1 | 480 |
198*4882a593Smuzhiyun * | 12 | 250 | 0 | 500 |
199*4882a593Smuzhiyun * | 4 | 100 | 0 | 600 |
200*4882a593Smuzhiyun * | 3 | 81 | 0 | 648 |
201*4882a593Smuzhiyun * | 3 | 88 | 0 | 704 |
202*4882a593Smuzhiyun * | 3 | 90 | 0 | 720 |
203*4882a593Smuzhiyun * | 3 | 100 | 0 | 800 |
204*4882a593Smuzhiyun * | 12 | 425 | 0 | 850 |
205*4882a593Smuzhiyun * | 4 | 150 | 0 | 900 |
206*4882a593Smuzhiyun * | 12 | 475 | 0 | 950 |
207*4882a593Smuzhiyun * | 6 | 250 | 0 | 1000 |
208*4882a593Smuzhiyun * -------------------------------------------
209*4882a593Smuzhiyun */
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /*
212*4882a593Smuzhiyun * pms could be calculated as the following.
213*4882a593Smuzhiyun * M * 24 / P * 2 ^ S = MHz
214*4882a593Smuzhiyun */
215*4882a593Smuzhiyun unsigned char p;
216*4882a593Smuzhiyun unsigned short m;
217*4882a593Smuzhiyun unsigned char s;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun unsigned int pll_stable_time;
220*4882a593Smuzhiyun unsigned long esc_clk;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun unsigned short stop_holding_cnt;
223*4882a593Smuzhiyun unsigned char bta_timeout;
224*4882a593Smuzhiyun unsigned short rx_timeout;
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun /*
228*4882a593Smuzhiyun * struct mipi_dsim_device - global interface for mipi-dsi driver.
229*4882a593Smuzhiyun *
230*4882a593Smuzhiyun * @dsim_config: infomation for configuring mipi-dsi controller.
231*4882a593Smuzhiyun * @master_ops: callbacks to mipi-dsi operations.
232*4882a593Smuzhiyun * @dsim_lcd_dev: pointer to activated ddi device.
233*4882a593Smuzhiyun * (it would be registered by mipi-dsi driver.)
234*4882a593Smuzhiyun * @dsim_lcd_drv: pointer to activated_ddi driver.
235*4882a593Smuzhiyun * (it would be registered by mipi-dsi driver.)
236*4882a593Smuzhiyun * @state: specifies status of MIPI-DSI controller.
237*4882a593Smuzhiyun * the status could be RESET, INIT, STOP, HSCLKEN and ULPS.
238*4882a593Smuzhiyun * @data_lane: specifiec enabled data lane number.
239*4882a593Smuzhiyun * this variable would be set by driver according to e_no_data_lane
240*4882a593Smuzhiyun * automatically.
241*4882a593Smuzhiyun * @e_clk_src: select byte clock source.
242*4882a593Smuzhiyun * @pd: pointer to MIPI-DSI driver platform data.
243*4882a593Smuzhiyun */
244*4882a593Smuzhiyun struct mipi_dsim_device {
245*4882a593Smuzhiyun struct mipi_dsim_config *dsim_config;
246*4882a593Smuzhiyun struct mipi_dsim_master_ops *master_ops;
247*4882a593Smuzhiyun struct mipi_dsim_lcd_device *dsim_lcd_dev;
248*4882a593Smuzhiyun struct mipi_dsim_lcd_driver *dsim_lcd_drv;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun unsigned int state;
251*4882a593Smuzhiyun unsigned int data_lane;
252*4882a593Smuzhiyun enum mipi_dsim_byte_clk_src e_clk_src;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun struct exynos_platform_mipi_dsim *pd;
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun /*
258*4882a593Smuzhiyun * struct exynos_platform_mipi_dsim - interface to platform data
259*4882a593Smuzhiyun * for mipi-dsi driver.
260*4882a593Smuzhiyun *
261*4882a593Smuzhiyun * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver.
262*4882a593Smuzhiyun * lcd panel driver searched would be actived.
263*4882a593Smuzhiyun * @dsim_config: pointer of structure for configuring mipi-dsi controller.
264*4882a593Smuzhiyun * @lcd_panel_info: pointer for lcd panel specific structure.
265*4882a593Smuzhiyun * this structure specifies width, height, timing and polarity and so on.
266*4882a593Smuzhiyun * @lcd_power: callback pointer for enabling or disabling lcd power.
267*4882a593Smuzhiyun * @mipi_power: callback pointer for enabling or disabling mipi power.
268*4882a593Smuzhiyun * @phy_enable: pointer to a callback controlling D-PHY enable/reset
269*4882a593Smuzhiyun */
270*4882a593Smuzhiyun struct exynos_platform_mipi_dsim {
271*4882a593Smuzhiyun char lcd_panel_name[PANEL_NAME_SIZE];
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun struct mipi_dsim_config *dsim_config;
274*4882a593Smuzhiyun void *lcd_panel_info;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun int (*lcd_power)(void);
277*4882a593Smuzhiyun int (*mipi_power)(void);
278*4882a593Smuzhiyun void (*phy_enable)(unsigned int dev_index, unsigned int enable);
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun /*
282*4882a593Smuzhiyun * struct mipi_dsim_master_ops - callbacks to mipi-dsi operations.
283*4882a593Smuzhiyun *
284*4882a593Smuzhiyun * @cmd_write: transfer command to lcd panel at LP mode.
285*4882a593Smuzhiyun * @cmd_read: read command from rx register.
286*4882a593Smuzhiyun * @get_dsim_frame_done: get the status that all screen data have been
287*4882a593Smuzhiyun * transferred to mipi-dsi.
288*4882a593Smuzhiyun * @clear_dsim_frame_done: clear frame done status.
289*4882a593Smuzhiyun * @get_fb_frame_done: get frame done status of display controller.
290*4882a593Smuzhiyun * @trigger: trigger display controller.
291*4882a593Smuzhiyun * - this one would be used only in case of CPU mode.
292*4882a593Smuzhiyun */
293*4882a593Smuzhiyun struct mipi_dsim_master_ops {
294*4882a593Smuzhiyun int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id,
295*4882a593Smuzhiyun const unsigned char *data0, unsigned int data1);
296*4882a593Smuzhiyun int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id,
297*4882a593Smuzhiyun unsigned int data0, unsigned int data1);
298*4882a593Smuzhiyun int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim);
299*4882a593Smuzhiyun int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun int (*get_fb_frame_done)(void);
302*4882a593Smuzhiyun void (*trigger)(struct fb_info *info);
303*4882a593Smuzhiyun };
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /*
306*4882a593Smuzhiyun * device structure for mipi-dsi based lcd panel.
307*4882a593Smuzhiyun *
308*4882a593Smuzhiyun * @name: name of the device to use with this device, or an
309*4882a593Smuzhiyun * alias for that name.
310*4882a593Smuzhiyun * @id: id of device to be registered.
311*4882a593Smuzhiyun * @bus_id: bus id for identifing connected bus
312*4882a593Smuzhiyun * and this bus id should be same as id of mipi_dsim_device.
313*4882a593Smuzhiyun * @master: pointer to mipi-dsi master device object.
314*4882a593Smuzhiyun * @platform_data: lcd panel specific platform data.
315*4882a593Smuzhiyun */
316*4882a593Smuzhiyun struct mipi_dsim_lcd_device {
317*4882a593Smuzhiyun char *name;
318*4882a593Smuzhiyun int id;
319*4882a593Smuzhiyun int bus_id;
320*4882a593Smuzhiyun int reverse_panel;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun struct mipi_dsim_device *master;
323*4882a593Smuzhiyun struct exynos_platform_mipi_dsim *platform_data;
324*4882a593Smuzhiyun };
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun /*
327*4882a593Smuzhiyun * driver structure for mipi-dsi based lcd panel.
328*4882a593Smuzhiyun *
329*4882a593Smuzhiyun * this structure should be registered by lcd panel driver.
330*4882a593Smuzhiyun * mipi-dsi driver seeks lcd panel registered through name field
331*4882a593Smuzhiyun * and calls these callback functions in appropriate time.
332*4882a593Smuzhiyun *
333*4882a593Smuzhiyun * @name: name of the driver to use with this device, or an
334*4882a593Smuzhiyun * alias for that name.
335*4882a593Smuzhiyun * @id: id of driver to be registered.
336*4882a593Smuzhiyun * this id would be used for finding device object registered.
337*4882a593Smuzhiyun * @mipi_panel_init: callback pointer for initializing lcd panel based on mipi
338*4882a593Smuzhiyun * dsi interface.
339*4882a593Smuzhiyun * @mipi_display_on: callback pointer for lcd panel display on.
340*4882a593Smuzhiyun */
341*4882a593Smuzhiyun struct mipi_dsim_lcd_driver {
342*4882a593Smuzhiyun char *name;
343*4882a593Smuzhiyun int id;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun int (*mipi_panel_init)(struct mipi_dsim_device *dsim_dev);
346*4882a593Smuzhiyun void (*mipi_display_on)(struct mipi_dsim_device *dsim_dev);
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun #ifdef CONFIG_EXYNOS_MIPI_DSIM
350*4882a593Smuzhiyun int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd);
351*4882a593Smuzhiyun #else
exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim * dsim_pd)352*4882a593Smuzhiyun static inline int exynos_mipi_dsi_init(
353*4882a593Smuzhiyun struct exynos_platform_mipi_dsim *dsim_pd)
354*4882a593Smuzhiyun {
355*4882a593Smuzhiyun return 0;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun #endif
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun /*
360*4882a593Smuzhiyun * register mipi_dsim_lcd_driver object defined by lcd panel driver
361*4882a593Smuzhiyun * to mipi-dsi driver.
362*4882a593Smuzhiyun */
363*4882a593Smuzhiyun int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver
364*4882a593Smuzhiyun *lcd_drv);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun /*
367*4882a593Smuzhiyun * register mipi_dsim_lcd_device to mipi-dsi master.
368*4882a593Smuzhiyun */
369*4882a593Smuzhiyun int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
370*4882a593Smuzhiyun *lcd_dev);
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
373*4882a593Smuzhiyun struct vidinfo;
374*4882a593Smuzhiyun void exynos_init_dsim_platform_data(struct vidinfo *vid);
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun /* panel driver init based on mipi dsi interface */
377*4882a593Smuzhiyun void s6e8ax0_init(void);
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun extern int mipi_power(void);
380*4882a593Smuzhiyun #endif /* _DSIM_H */
381