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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/input/rmi4/
H A Drmi_spi.txt1 Synaptics RMI4 SPI Device Binding
5 bindings for devices using the SPI transport driver. Complete documentation
10 - compatible: syna,rmi4-spi
11 - reg: Chip select address for the device
12 - #address-cells: Set to 1 to indicate that the function child nodes
14 - #size-cells: Set to 0 to indicate that the function child nodes do not
18 - interrupts: interrupt which the rmi device is connected to.
19 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
21 - spi-rx-delay-us: microsecond delay after a read transfer.
22 - spi-tx-delay-us: microsecond delay after a write transfer.
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/OK3568_Linux_fs/kernel/drivers/iio/gyro/
H A Dadxrs450.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/delay.h>
14 #include <linux/spi/spi.h>
25 /* The MSB for the spi commands */
67 * struct adxrs450_state - device instance specific data
68 * @us: actual spi_device
69 * @buf_lock: mutex to protect tx and rx
71 * @rx: receive buffer
74 struct spi_device *us; member
77 __be32 rx; member
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/OK3568_Linux_fs/kernel/drivers/spi/
H A Dspi-dw-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
14 #include <linux/platform_data/dma-dw.h>
15 #include <linux/spi/spi.h>
18 #include "spi-dw.h"
29 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
32 chan->private = s; in dw_spi_dma_chan_filter()
42 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
44 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
50 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
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H A Dspi-dw-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Designware SPI core controller driver (refer pxa2xx_spi.c)
8 #include <linux/dma-mapping.h>
13 #include <linux/delay.h>
15 #include <linux/spi/spi.h>
16 #include <linux/spi/spi-mem.h>
20 #include "spi-dw.h"
29 u32 rx_sample_dly; /* RX sample delay */
63 snprintf(name, 32, "dw_spi%d", dws->master->bus_num); in dw_spi_debugfs_init()
64 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
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H A Dspi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Addy Ke <addy.ke@rock-chips.com>
9 #include <linux/delay.h>
18 #include <linux/spi/spi.h>
22 #define DRIVER_NAME "rockchip-spi"
29 /* SPI register offsets */
71 /* ss_n to sclk_out delay */
158 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
164 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
169 /* 2 for native cs, 2 for cs-gpio */
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H A Dspidev-rkmst.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <linux/delay.h>
17 #include <linux/spi/spi.h>
19 #include <linux/platform_data/spi-rockchip.h>
40 struct spi_device *spi; member
55 spidev->ready_status = status; in spidev_mst_slave_ready_status()
69 return spidev->ready_status; in spidev_mst_check_slave_ready()
81 dev_err(&spidev->spi->dev, "timeout and reset slave\n"); in spidev_mst_wait_for_slave_ready()
83 return -ETIMEDOUT; in spidev_mst_wait_for_slave_ready()
91 struct spi_device *spi = spidev->spi; in spidev_mst_write() local
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H A Dspi-rockchip-test.c1 /*drivers/spi/spi-rockchip-test.c -spi test driver
10 /* how to test spi
24 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
30 #include <linux/spi/spi.h>
36 #include <linux/platform_data/spi-rockchip.h>
45 struct spi_device *spi; member
57 int ret = -1; in spi_write_slt()
58 struct spi_device *spi = NULL; in spi_write_slt() local
72 spi = g_spi_test_data[id]->spi; in spi_write_slt()
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H A Dspi-mpc512x-psc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC512x PSC in SPI mode driver.
7 * Hongjun Chen <hong-jun.chen@freescale.com>
22 #include <linux/delay.h>
24 #include <linux/spi/spi.h>
40 switch (mps->type) { \
42 struct mpc52xx_psc __iomem *psc = mps->psc; \
43 __ret = &psc->regname; \
47 struct mpc5125_psc __iomem *psc = mps->psc; \
48 __ret = &psc->regname; \
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H A Dspi-sifive.c1 // SPDX-License-Identifier: GPL-2.0
5 // SiFive SPI controller driver (master mode only)
15 #include <linux/spi/spi.h>
31 #define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
32 #define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
35 #define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
37 #define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
38 #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
39 #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
96 struct completion done; /* wake-up from interrupt */
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Generic Binding
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-[0-9a-f])*$"
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/OK3568_Linux_fs/kernel/net/nfc/nci/
H A Dspi.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/spi/spi.h>
12 #include <linux/crc-ccitt.h>
37 /* a NULL skb means we just want the SPI chip select line to raise */ in __nci_spi_send()
39 t.tx_buf = skb->data; in __nci_spi_send()
40 t.len = skb->len; in __nci_spi_send()
47 t.delay.value = nspi->xfer_udelay; in __nci_spi_send()
48 t.delay.unit = SPI_DELAY_UNIT_USECS; in __nci_spi_send()
49 t.speed_hz = nspi->xfer_speed_hz; in __nci_spi_send()
54 return spi_sync(nspi->spi, &m); in __nci_spi_send()
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dste-u300.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree for the ST-Ericsson U300 Machine and SoC
6 /dts-v1/;
9 model = "ST-Ericsson U300";
11 #address-cells = <1>;
12 #size-cells = <1>;
30 vana15-supply = <&ab3100_ldo_d_reg>;
35 compatible = "stericsson,u300-syscon", "syscon";
38 #clock-cells = <0>;
39 compatible = "fixed-clock";
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H A Drv1109-38-v10-spi-nand.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "rv1126-ipc.dtsi"
11 model = "Rockchip RV1109 38 V10 SPI NAND DDR3 Board";
12 compatible = "rockchip,rv1109-38-v10-spi-nand", "rockchip,rv1109";
18 /delete-node/ vdd-npu;
19 /delete-node/ vdd-vepu;
24 ircut-open-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
25 ircut-close-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
26 pinctrl-names = "default";
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H A Drv1126-38x38-v10-spi-nor.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "rv1126-ipc.dtsi"
9 #include <dt-bindings/input/input.h>
12 model = "Rockchip RV1126 38x38 V10 SPI NOR DDR3 Board";
13 compatible = "rockchip,rv1126-38x38-v10-spi-nor", "rockchip,rv1126";
19 /delete-node/ vdd-npu;
20 /delete-node/ vdd-vepu;
22 vcc_1v8: vcc-1v8 {
23 compatible = "regulator-fixed";
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/OK3568_Linux_fs/u-boot/drivers/spi/
H A Dtegra210_qspi.c6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch-tegra/clk_rst.h>
14 #include <spi.h>
80 u32 rsvd[56]; /* 028-107 reserved */
82 u32 rsvd2[31]; /* 10c-187 reserved */
98 struct tegra_spi_platdata *plat = bus->platdata; in tegra210_qspi_ofdata_to_platdata()
99 const void *blob = gd->fdt_blob; in tegra210_qspi_ofdata_to_platdata()
102 plat->base = devfdt_get_addr(bus); in tegra210_qspi_ofdata_to_platdata()
103 plat->periph_id = clock_decode_periph_id(bus); in tegra210_qspi_ofdata_to_platdata()
105 if (plat->periph_id == PERIPH_ID_NONE) { in tegra210_qspi_ofdata_to_platdata()
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H A Drk_spi.c2 * spi driver for rockchip
6 * (C) Copyright 2008-2013 Rockchip Electronics
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <dt-structs.h>
17 #include <spi.h>
38 s32 frequency; /* Default clock frequency, -1 for none */
40 uint deactivate_delay_us; /* Delay to wait after deactivate */
41 uint activate_delay_us; /* Delay to wait after activate */
56 u32 rsd; /* Rx sample delay cycles */
67 debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0)); in rkspi_dump_regs()
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/OK3568_Linux_fs/kernel/include/linux/iio/imu/
H A Dadis.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
12 #include <linux/spi/spi.h>
25 * struct adis_timeouts - ADIS chip variant timeouts
26 * @reset_ms - Wait time after rst pin goes inactive
27 * @sw_reset_ms - Wait time after sw reset command
28 * @self_test_ms - Wait time after self test command
36 * struct adis_data - ADIS chip variant specific data
37 * @read_delay: SPI delay for read operations in us
38 * @write_delay: SPI delay for write operations in us
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/OK3568_Linux_fs/kernel/Documentation/networking/
H A Dpktgen.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Enable CONFIG_NET_PKTGEN to compile and build pktgen either in-kernel
31 overload type of benchmarking, as this could hurt the normal use-case.
35 # ethtool -G ethX tx 1024
43 TX ring cause delay. Drivers usually delay cleaning up the
44 ring-buffers for various performance reasons, and packets stalling
48 (Intel 82599 chip). This driver (ixgbe) combines TX+RX ring cleanups,
49 and the cleanup interval is affected by the ethtool --coalesce setting
50 of parameter "rx-usecs".
54 # ethtool -C ethX rx-usecs 30
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/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 bank-width = <2>;
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/
H A Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&intc>;
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H A Dqcs404.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
6 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/thermal/thermal.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
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/OK3568_Linux_fs/kernel/drivers/iio/adc/
H A Dmax1241.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MAX1241 low-power, 12-bit serial ADC
5 * Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX1240-MAX1241.pdf
8 #include <linux/delay.h>
13 #include <linux/spi/spi.h>
23 struct spi_device *spi; member
47 * tconv us. in max1241_read()
51 .delay.value = 8, in max1241_read()
52 .delay.unit = SPI_DELAY_UNIT_USECS, in max1241_read()
55 * Then read two bytes of data in our RX buffer. in max1241_read()
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/nvidia/
H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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/OK3568_Linux_fs/u-boot/drivers/mtd/spi/
H A Dsandbox.c2 * Simulate a SPI flash
4 * Copyright (c) 2011-2013 The Chromium OS Authors.
8 * Licensed under the GPL-2 or later.
16 #include <spi.h>
23 #include <asm/spi.h>
25 #include <dm/device-internal.h>
27 #include <dm/uclass-internal.h>
32 * The different states that our SPI flash transitions between.
34 * the SPI bus could possibly call down into us multiple times.
37 SF_CMD, /* default state -- we're awaiting a command */
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h6-pine-h64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-h6.dtsi"
7 #include "sun50i-h6-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
13 compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
22 stdout-path = "serial0:115200n8";
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <32768>;
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