1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the MPC5121e based ac14xx board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2012 Anatolij Gustschin <agust@denx.de> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "mpc5121.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "ac14xx"; 13*4882a593Smuzhiyun compatible = "ifm,ac14xx", "fsl,mpc5121"; 14*4882a593Smuzhiyun #address-cells = <1>; 15*4882a593Smuzhiyun #size-cells = <1>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun aliases { 18*4882a593Smuzhiyun serial0 = &serial0; 19*4882a593Smuzhiyun serial1 = &serial7; 20*4882a593Smuzhiyun spi4 = &spi4; 21*4882a593Smuzhiyun spi5 = &spi5; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun cpus { 25*4882a593Smuzhiyun PowerPC,5121@0 { 26*4882a593Smuzhiyun timebase-frequency = <40000000>; /* 40 MHz (csb/4) */ 27*4882a593Smuzhiyun bus-frequency = <160000000>; /* 160 MHz csb bus */ 28*4882a593Smuzhiyun clock-frequency = <400000000>; /* 400 MHz ppc core */ 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun memory { 33*4882a593Smuzhiyun reg = <0x00000000 0x10000000>; /* 256MB at 0 */ 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun nfc@40000000 { 37*4882a593Smuzhiyun status = "disabled"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun localbus@80000020 { 41*4882a593Smuzhiyun ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */ 42*4882a593Smuzhiyun 0x1 0x0 0xe0000000 0x00010000 /* CS1: FRAM */ 43*4882a593Smuzhiyun 0x2 0x0 0xe0100000 0x00080000 /* CS2: asi1 */ 44*4882a593Smuzhiyun 0x3 0x0 0xe0300000 0x00020000 /* CS3: comm */ 45*4882a593Smuzhiyun 0x5 0x0 0xe0400000 0x00010000 /* CS5: safety */ 46*4882a593Smuzhiyun 0x6 0x0 0xe0200000 0x00080000>; /* CS6: asi2 */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun flash@0,0 { 49*4882a593Smuzhiyun compatible = "cfi-flash"; 50*4882a593Smuzhiyun reg = <0 0x00000000 0x04000000>; 51*4882a593Smuzhiyun #address-cells = <1>; 52*4882a593Smuzhiyun #size-cells = <1>; 53*4882a593Smuzhiyun bank-width = <2>; 54*4882a593Smuzhiyun device-width = <2>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun partition@0 { 57*4882a593Smuzhiyun label = "dtb-kernel-production"; 58*4882a593Smuzhiyun reg = <0x00000000 0x00400000>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun partition@1 { 61*4882a593Smuzhiyun label = "filesystem-production"; 62*4882a593Smuzhiyun reg = <0x00400000 0x03400000>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun partition@2 { 66*4882a593Smuzhiyun label = "recovery"; 67*4882a593Smuzhiyun reg = <0x03800000 0x00700000>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun partition@3 { 71*4882a593Smuzhiyun label = "uboot-code"; 72*4882a593Smuzhiyun reg = <0x03f00000 0x00040000>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun partition@4 { 75*4882a593Smuzhiyun label = "uboot-env1"; 76*4882a593Smuzhiyun reg = <0x03f40000 0x00020000>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun partition@5 { 79*4882a593Smuzhiyun label = "uboot-env2"; 80*4882a593Smuzhiyun reg = <0x03f60000 0x00020000>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun fram@1,0 { 85*4882a593Smuzhiyun compatible = "ifm,ac14xx-fram", "linux,uio-pdrv-genirq"; 86*4882a593Smuzhiyun reg = <1 0x00000000 0x00010000>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun asi@2,0 { 90*4882a593Smuzhiyun /* masters mapping: CS, CS offset, size */ 91*4882a593Smuzhiyun reg = <2 0x00000000 0x00080000 92*4882a593Smuzhiyun 6 0x00000000 0x00080000>; 93*4882a593Smuzhiyun #address-cells = <1>; 94*4882a593Smuzhiyun #size-cells = <1>; 95*4882a593Smuzhiyun compatible = "ifm,ac14xx-asi-fpga"; 96*4882a593Smuzhiyun gpios = < 97*4882a593Smuzhiyun &gpio_pic 26 0 /* prog */ 98*4882a593Smuzhiyun &gpio_pic 27 0 /* done */ 99*4882a593Smuzhiyun &gpio_pic 10 0 /* reset */ 100*4882a593Smuzhiyun >; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun master@1 { 103*4882a593Smuzhiyun interrupts = <20 0x2>; 104*4882a593Smuzhiyun interrupt-parent = <&gpio_pic>; 105*4882a593Smuzhiyun chipselect = <2 0x00009000 0x00009100>; 106*4882a593Smuzhiyun label = "AS-i master 1"; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun master@2 { 110*4882a593Smuzhiyun interrupts = <21 0x2>; 111*4882a593Smuzhiyun interrupt-parent = <&gpio_pic>; 112*4882a593Smuzhiyun chipselect = <6 0x00009000 0x00009100>; 113*4882a593Smuzhiyun label = "AS-i master 2"; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun netx@3,0 { 118*4882a593Smuzhiyun compatible = "ifm,netx"; 119*4882a593Smuzhiyun reg = <0x3 0x00000000 0x00020000>; 120*4882a593Smuzhiyun chipselect = <3 0x00101140 0x00203100>; 121*4882a593Smuzhiyun interrupts = <17 0x8>; 122*4882a593Smuzhiyun gpios = <&gpio_pic 15 0>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun safety@5,0 { 126*4882a593Smuzhiyun compatible = "ifm,safety"; 127*4882a593Smuzhiyun reg = <0x5 0x00000000 0x00010000>; 128*4882a593Smuzhiyun chipselect = <5 0x00009000 0x00009100>; 129*4882a593Smuzhiyun interrupts = <22 0x2>; 130*4882a593Smuzhiyun interrupt-parent = <&gpio_pic>; 131*4882a593Smuzhiyun gpios = < 132*4882a593Smuzhiyun &gpio_pic 12 0 /* prog */ 133*4882a593Smuzhiyun &gpio_pic 11 0 /* done */ 134*4882a593Smuzhiyun >; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun clocks { 139*4882a593Smuzhiyun osc { 140*4882a593Smuzhiyun clock-frequency = <25000000>; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun soc@80000000 { 145*4882a593Smuzhiyun bus-frequency = <80000000>; /* 80 MHz ips bus */ 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun clock@f00 { 148*4882a593Smuzhiyun compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock"; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* 152*4882a593Smuzhiyun * GPIO PIC: 153*4882a593Smuzhiyun * interrupts cell = <pin nr, sense> 154*4882a593Smuzhiyun * sense == 8: Level, low assertion 155*4882a593Smuzhiyun * sense == 2: Edge, high-to-low change 156*4882a593Smuzhiyun */ 157*4882a593Smuzhiyun gpio_pic: gpio@1100 { 158*4882a593Smuzhiyun gpio-controller; 159*4882a593Smuzhiyun #gpio-cells = <2>; 160*4882a593Smuzhiyun interrupt-controller; 161*4882a593Smuzhiyun #interrupt-cells = <2>; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun sdhc@1500 { 165*4882a593Smuzhiyun cd-gpios = <&gpio_pic 23 0>; /* card detect */ 166*4882a593Smuzhiyun wp-gpios = <&gpio_pic 24 0>; /* write protect */ 167*4882a593Smuzhiyun wp-inverted; /* WP active high */ 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun i2c@1700 { 171*4882a593Smuzhiyun /* use Fast-mode */ 172*4882a593Smuzhiyun clock-frequency = <400000>; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun at24@30 { 175*4882a593Smuzhiyun compatible = "atmel,24c01"; 176*4882a593Smuzhiyun reg = <0x30>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun at24@31 { 180*4882a593Smuzhiyun compatible = "atmel,24c01"; 181*4882a593Smuzhiyun reg = <0x31>; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun temp@48 { 185*4882a593Smuzhiyun compatible = "ad,ad7414"; 186*4882a593Smuzhiyun reg = <0x48>; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun at24@50 { 190*4882a593Smuzhiyun compatible = "atmel,24c01"; 191*4882a593Smuzhiyun reg = <0x50>; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun at24@51 { 195*4882a593Smuzhiyun compatible = "atmel,24c01"; 196*4882a593Smuzhiyun reg = <0x51>; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun at24@52 { 200*4882a593Smuzhiyun compatible = "atmel,24c01"; 201*4882a593Smuzhiyun reg = <0x52>; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun at24@53 { 205*4882a593Smuzhiyun compatible = "atmel,24c01"; 206*4882a593Smuzhiyun reg = <0x53>; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun at24@54 { 210*4882a593Smuzhiyun compatible = "atmel,24c01"; 211*4882a593Smuzhiyun reg = <0x54>; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun at24@55 { 215*4882a593Smuzhiyun compatible = "atmel,24c01"; 216*4882a593Smuzhiyun reg = <0x55>; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun at24@56 { 220*4882a593Smuzhiyun compatible = "atmel,24c01"; 221*4882a593Smuzhiyun reg = <0x56>; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun at24@57 { 225*4882a593Smuzhiyun compatible = "atmel,24c01"; 226*4882a593Smuzhiyun reg = <0x57>; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun rtc@68 { 230*4882a593Smuzhiyun compatible = "st,m41t00"; 231*4882a593Smuzhiyun reg = <0x68>; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun axe_pic: axe-base@2000 { 236*4882a593Smuzhiyun compatible = "fsl,mpc5121-axe-base"; 237*4882a593Smuzhiyun reg = <0x2000 0x100>; 238*4882a593Smuzhiyun interrupts = <42 0x8>; 239*4882a593Smuzhiyun interrupt-controller; 240*4882a593Smuzhiyun #interrupt-cells = <2>; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun axe-app { 244*4882a593Smuzhiyun compatible = "fsl,mpc5121-axe-app"; 245*4882a593Smuzhiyun interrupt-parent = <&axe_pic>; 246*4882a593Smuzhiyun interrupts = < 247*4882a593Smuzhiyun /* soft interrupts */ 248*4882a593Smuzhiyun 0 0x0 1 0x0 2 0x0 3 0x0 249*4882a593Smuzhiyun 4 0x0 5 0x0 6 0x0 7 0x0 250*4882a593Smuzhiyun /* fifo interrupts */ 251*4882a593Smuzhiyun 8 0x0 9 0x0 10 0x0 11 0x0 252*4882a593Smuzhiyun >; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun display@2100 { 256*4882a593Smuzhiyun edid = [00 FF FF FF FF FF FF 00 14 94 00 00 00 00 00 00 257*4882a593Smuzhiyun 0A 12 01 03 80 1C 23 78 CA 88 FF 94 52 54 8E 27 258*4882a593Smuzhiyun 1E 4C 50 00 00 00 01 01 01 01 01 01 01 01 01 01 259*4882a593Smuzhiyun 01 01 01 01 01 01 FB 00 B0 14 00 DC 05 00 08 04 260*4882a593Smuzhiyun 21 00 1C 23 00 00 00 18 00 00 00 FD 00 38 3C 1F 261*4882a593Smuzhiyun 3C 01 0A 20 20 20 20 20 20 20 00 00 00 FC 00 45 262*4882a593Smuzhiyun 54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10 263*4882a593Smuzhiyun 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5]; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun can@2300 { 267*4882a593Smuzhiyun status = "disabled"; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun can@2380 { 271*4882a593Smuzhiyun status = "disabled"; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun viu@2400 { 275*4882a593Smuzhiyun status = "disabled"; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun mdio@2800 { 279*4882a593Smuzhiyun phy0: ethernet-phy@1f { 280*4882a593Smuzhiyun compatible = "smsc,lan8700"; 281*4882a593Smuzhiyun reg = <0x1f>; 282*4882a593Smuzhiyun }; 283*4882a593Smuzhiyun }; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun enet: ethernet@2800 { 286*4882a593Smuzhiyun phy-handle = <&phy0>; 287*4882a593Smuzhiyun }; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun usb@3000 { 290*4882a593Smuzhiyun status = "disabled"; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun usb@4000 { 294*4882a593Smuzhiyun status = "disabled"; 295*4882a593Smuzhiyun }; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun /* PSC3 serial port A, aka ttyPSC0 */ 298*4882a593Smuzhiyun serial0: psc@11300 { 299*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 300*4882a593Smuzhiyun fsl,rx-fifo-size = <512>; 301*4882a593Smuzhiyun fsl,tx-fifo-size = <512>; 302*4882a593Smuzhiyun }; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun /* PSC4 in SPI mode */ 305*4882a593Smuzhiyun spi4: psc@11400 { 306*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc"; 307*4882a593Smuzhiyun fsl,rx-fifo-size = <768>; 308*4882a593Smuzhiyun fsl,tx-fifo-size = <768>; 309*4882a593Smuzhiyun #address-cells = <1>; 310*4882a593Smuzhiyun #size-cells = <0>; 311*4882a593Smuzhiyun num-cs = <1>; 312*4882a593Smuzhiyun cs-gpios = <&gpio_pic 25 0>; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun flash: m25p128@0 { 315*4882a593Smuzhiyun compatible = "st,m25p128"; 316*4882a593Smuzhiyun spi-max-frequency = <20000000>; 317*4882a593Smuzhiyun reg = <0>; 318*4882a593Smuzhiyun #address-cells = <1>; 319*4882a593Smuzhiyun #size-cells = <1>; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun partition@0 { 322*4882a593Smuzhiyun label = "spi-flash0"; 323*4882a593Smuzhiyun reg = <0x00000000 0x01000000>; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun /* PSC5 in SPI mode */ 329*4882a593Smuzhiyun spi5: psc@11500 { 330*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc"; 331*4882a593Smuzhiyun fsl,mode = "spi-master"; 332*4882a593Smuzhiyun fsl,rx-fifo-size = <128>; 333*4882a593Smuzhiyun fsl,tx-fifo-size = <128>; 334*4882a593Smuzhiyun #address-cells = <1>; 335*4882a593Smuzhiyun #size-cells = <0>; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun lcd@0 { 338*4882a593Smuzhiyun compatible = "ilitek,ili922x"; 339*4882a593Smuzhiyun reg = <0>; 340*4882a593Smuzhiyun spi-max-frequency = <100000>; 341*4882a593Smuzhiyun spi-cpol; 342*4882a593Smuzhiyun spi-cpha; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun /* PSC7 serial port C, aka ttyPSC2 */ 347*4882a593Smuzhiyun serial7: psc@11700 { 348*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 349*4882a593Smuzhiyun fsl,rx-fifo-size = <512>; 350*4882a593Smuzhiyun fsl,tx-fifo-size = <512>; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun matrix_keypad@0 { 354*4882a593Smuzhiyun compatible = "gpio-matrix-keypad"; 355*4882a593Smuzhiyun debounce-delay-ms = <5>; 356*4882a593Smuzhiyun col-scan-delay-us = <1>; 357*4882a593Smuzhiyun gpio-activelow; 358*4882a593Smuzhiyun col-gpios-binary; 359*4882a593Smuzhiyun col-switch-delay-ms = <200>; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun col-gpios = <&gpio_pic 1 0>; /* pin1 */ 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun row-gpios = <&gpio_pic 2 0 /* pin2 */ 364*4882a593Smuzhiyun &gpio_pic 3 0 /* pin3 */ 365*4882a593Smuzhiyun &gpio_pic 4 0>; /* pin4 */ 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun linux,keymap = <0x0000006e /* FN LEFT */ 368*4882a593Smuzhiyun 0x01000067 /* UP */ 369*4882a593Smuzhiyun 0x02000066 /* FN RIGHT */ 370*4882a593Smuzhiyun 0x00010069 /* LEFT */ 371*4882a593Smuzhiyun 0x0101006a /* DOWN */ 372*4882a593Smuzhiyun 0x0201006c>; /* RIGHT */ 373*4882a593Smuzhiyun }; 374*4882a593Smuzhiyun }; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun leds { 377*4882a593Smuzhiyun compatible = "gpio-leds"; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun backlight { 380*4882a593Smuzhiyun label = "backlight"; 381*4882a593Smuzhiyun gpios = <&gpio_pic 0 0>; 382*4882a593Smuzhiyun default-state = "keep"; 383*4882a593Smuzhiyun }; 384*4882a593Smuzhiyun green { 385*4882a593Smuzhiyun label = "green"; 386*4882a593Smuzhiyun gpios = <&gpio_pic 18 0>; 387*4882a593Smuzhiyun default-state = "keep"; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun red { 390*4882a593Smuzhiyun label = "red"; 391*4882a593Smuzhiyun gpios = <&gpio_pic 19 0>; 392*4882a593Smuzhiyun default-state = "keep"; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun}; 396