xref: /OK3568_Linux_fs/kernel/drivers/iio/gyro/adxrs450.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * ADXRS450/ADXRS453 Digital Output Gyroscope Driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2011 Analog Devices Inc.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/interrupt.h>
9*4882a593Smuzhiyun #include <linux/irq.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/mutex.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/spi/spi.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/sysfs.h>
17*4882a593Smuzhiyun #include <linux/list.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <linux/iio/iio.h>
21*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define ADXRS450_STARTUP_DELAY	50 /* ms */
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun /* The MSB for the spi commands */
26*4882a593Smuzhiyun #define ADXRS450_SENSOR_DATA    (0x20 << 24)
27*4882a593Smuzhiyun #define ADXRS450_WRITE_DATA	(0x40 << 24)
28*4882a593Smuzhiyun #define ADXRS450_READ_DATA	(0x80 << 24)
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define ADXRS450_RATE1	0x00	/* Rate Registers */
31*4882a593Smuzhiyun #define ADXRS450_TEMP1	0x02	/* Temperature Registers */
32*4882a593Smuzhiyun #define ADXRS450_LOCST1	0x04	/* Low CST Memory Registers */
33*4882a593Smuzhiyun #define ADXRS450_HICST1	0x06	/* High CST Memory Registers */
34*4882a593Smuzhiyun #define ADXRS450_QUAD1	0x08	/* Quad Memory Registers */
35*4882a593Smuzhiyun #define ADXRS450_FAULT1	0x0A	/* Fault Registers */
36*4882a593Smuzhiyun #define ADXRS450_PID1	0x0C	/* Part ID Register 1 */
37*4882a593Smuzhiyun #define ADXRS450_SNH	0x0E	/* Serial Number Registers, 4 bytes */
38*4882a593Smuzhiyun #define ADXRS450_SNL	0x10
39*4882a593Smuzhiyun #define ADXRS450_DNC1	0x12	/* Dynamic Null Correction Registers */
40*4882a593Smuzhiyun /* Check bits */
41*4882a593Smuzhiyun #define ADXRS450_P	0x01
42*4882a593Smuzhiyun #define ADXRS450_CHK	0x02
43*4882a593Smuzhiyun #define ADXRS450_CST	0x04
44*4882a593Smuzhiyun #define ADXRS450_PWR	0x08
45*4882a593Smuzhiyun #define ADXRS450_POR	0x10
46*4882a593Smuzhiyun #define ADXRS450_NVM	0x20
47*4882a593Smuzhiyun #define ADXRS450_Q	0x40
48*4882a593Smuzhiyun #define ADXRS450_PLL	0x80
49*4882a593Smuzhiyun #define ADXRS450_UV	0x100
50*4882a593Smuzhiyun #define ADXRS450_OV	0x200
51*4882a593Smuzhiyun #define ADXRS450_AMP	0x400
52*4882a593Smuzhiyun #define ADXRS450_FAIL	0x800
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define ADXRS450_WRERR_MASK	(0x7 << 29)
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define ADXRS450_MAX_RX 4
57*4882a593Smuzhiyun #define ADXRS450_MAX_TX 4
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define ADXRS450_GET_ST(a)	((a >> 26) & 0x3)
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun enum {
62*4882a593Smuzhiyun 	ID_ADXRS450,
63*4882a593Smuzhiyun 	ID_ADXRS453,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /**
67*4882a593Smuzhiyun  * struct adxrs450_state - device instance specific data
68*4882a593Smuzhiyun  * @us:			actual spi_device
69*4882a593Smuzhiyun  * @buf_lock:		mutex to protect tx and rx
70*4882a593Smuzhiyun  * @tx:			transmit buffer
71*4882a593Smuzhiyun  * @rx:			receive buffer
72*4882a593Smuzhiyun  **/
73*4882a593Smuzhiyun struct adxrs450_state {
74*4882a593Smuzhiyun 	struct spi_device	*us;
75*4882a593Smuzhiyun 	struct mutex		buf_lock;
76*4882a593Smuzhiyun 	__be32			tx ____cacheline_aligned;
77*4882a593Smuzhiyun 	__be32			rx;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun /**
82*4882a593Smuzhiyun  * adxrs450_spi_read_reg_16() - read 2 bytes from a register pair
83*4882a593Smuzhiyun  * @indio_dev: device associated with child of actual iio_dev
84*4882a593Smuzhiyun  * @reg_address: the address of the lower of the two registers, which should be
85*4882a593Smuzhiyun  *	an even address, the second register's address is reg_address + 1.
86*4882a593Smuzhiyun  * @val: somewhere to pass back the value read
87*4882a593Smuzhiyun  **/
adxrs450_spi_read_reg_16(struct iio_dev * indio_dev,u8 reg_address,u16 * val)88*4882a593Smuzhiyun static int adxrs450_spi_read_reg_16(struct iio_dev *indio_dev,
89*4882a593Smuzhiyun 				    u8 reg_address,
90*4882a593Smuzhiyun 				    u16 *val)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	struct adxrs450_state *st = iio_priv(indio_dev);
93*4882a593Smuzhiyun 	u32 tx;
94*4882a593Smuzhiyun 	int ret;
95*4882a593Smuzhiyun 	struct spi_transfer xfers[] = {
96*4882a593Smuzhiyun 		{
97*4882a593Smuzhiyun 			.tx_buf = &st->tx,
98*4882a593Smuzhiyun 			.bits_per_word = 8,
99*4882a593Smuzhiyun 			.len = sizeof(st->tx),
100*4882a593Smuzhiyun 			.cs_change = 1,
101*4882a593Smuzhiyun 		}, {
102*4882a593Smuzhiyun 			.rx_buf = &st->rx,
103*4882a593Smuzhiyun 			.bits_per_word = 8,
104*4882a593Smuzhiyun 			.len = sizeof(st->rx),
105*4882a593Smuzhiyun 		},
106*4882a593Smuzhiyun 	};
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	mutex_lock(&st->buf_lock);
109*4882a593Smuzhiyun 	tx = ADXRS450_READ_DATA | (reg_address << 17);
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	if (!(hweight32(tx) & 1))
112*4882a593Smuzhiyun 		tx |= ADXRS450_P;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	st->tx = cpu_to_be32(tx);
115*4882a593Smuzhiyun 	ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
116*4882a593Smuzhiyun 	if (ret) {
117*4882a593Smuzhiyun 		dev_err(&st->us->dev, "problem while reading 16 bit register 0x%02x\n",
118*4882a593Smuzhiyun 				reg_address);
119*4882a593Smuzhiyun 		goto error_ret;
120*4882a593Smuzhiyun 	}
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	*val = (be32_to_cpu(st->rx) >> 5) & 0xFFFF;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun error_ret:
125*4882a593Smuzhiyun 	mutex_unlock(&st->buf_lock);
126*4882a593Smuzhiyun 	return ret;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun /**
130*4882a593Smuzhiyun  * adxrs450_spi_write_reg_16() - write 2 bytes data to a register pair
131*4882a593Smuzhiyun  * @indio_dev: device associated with child of actual actual iio_dev
132*4882a593Smuzhiyun  * @reg_address: the address of the lower of the two registers,which should be
133*4882a593Smuzhiyun  *	an even address, the second register's address is reg_address + 1.
134*4882a593Smuzhiyun  * @val: value to be written.
135*4882a593Smuzhiyun  **/
adxrs450_spi_write_reg_16(struct iio_dev * indio_dev,u8 reg_address,u16 val)136*4882a593Smuzhiyun static int adxrs450_spi_write_reg_16(struct iio_dev *indio_dev,
137*4882a593Smuzhiyun 				     u8 reg_address,
138*4882a593Smuzhiyun 				     u16 val)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun 	struct adxrs450_state *st = iio_priv(indio_dev);
141*4882a593Smuzhiyun 	u32 tx;
142*4882a593Smuzhiyun 	int ret;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	mutex_lock(&st->buf_lock);
145*4882a593Smuzhiyun 	tx = ADXRS450_WRITE_DATA | (reg_address << 17) | (val << 1);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	if (!(hweight32(tx) & 1))
148*4882a593Smuzhiyun 		tx |= ADXRS450_P;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	st->tx = cpu_to_be32(tx);
151*4882a593Smuzhiyun 	ret = spi_write(st->us, &st->tx, sizeof(st->tx));
152*4882a593Smuzhiyun 	if (ret)
153*4882a593Smuzhiyun 		dev_err(&st->us->dev, "problem while writing 16 bit register 0x%02x\n",
154*4882a593Smuzhiyun 			reg_address);
155*4882a593Smuzhiyun 	usleep_range(100, 1000); /* enforce sequential transfer delay 0.1ms */
156*4882a593Smuzhiyun 	mutex_unlock(&st->buf_lock);
157*4882a593Smuzhiyun 	return ret;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun /**
161*4882a593Smuzhiyun  * adxrs450_spi_sensor_data() - read 2 bytes sensor data
162*4882a593Smuzhiyun  * @indio_dev: device associated with child of actual iio_dev
163*4882a593Smuzhiyun  * @val: somewhere to pass back the value read
164*4882a593Smuzhiyun  **/
adxrs450_spi_sensor_data(struct iio_dev * indio_dev,s16 * val)165*4882a593Smuzhiyun static int adxrs450_spi_sensor_data(struct iio_dev *indio_dev, s16 *val)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun 	struct adxrs450_state *st = iio_priv(indio_dev);
168*4882a593Smuzhiyun 	int ret;
169*4882a593Smuzhiyun 	struct spi_transfer xfers[] = {
170*4882a593Smuzhiyun 		{
171*4882a593Smuzhiyun 			.tx_buf = &st->tx,
172*4882a593Smuzhiyun 			.bits_per_word = 8,
173*4882a593Smuzhiyun 			.len = sizeof(st->tx),
174*4882a593Smuzhiyun 			.cs_change = 1,
175*4882a593Smuzhiyun 		}, {
176*4882a593Smuzhiyun 			.rx_buf = &st->rx,
177*4882a593Smuzhiyun 			.bits_per_word = 8,
178*4882a593Smuzhiyun 			.len = sizeof(st->rx),
179*4882a593Smuzhiyun 		},
180*4882a593Smuzhiyun 	};
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	mutex_lock(&st->buf_lock);
183*4882a593Smuzhiyun 	st->tx = cpu_to_be32(ADXRS450_SENSOR_DATA);
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
186*4882a593Smuzhiyun 	if (ret) {
187*4882a593Smuzhiyun 		dev_err(&st->us->dev, "Problem while reading sensor data\n");
188*4882a593Smuzhiyun 		goto error_ret;
189*4882a593Smuzhiyun 	}
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	*val = (be32_to_cpu(st->rx) >> 10) & 0xFFFF;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun error_ret:
194*4882a593Smuzhiyun 	mutex_unlock(&st->buf_lock);
195*4882a593Smuzhiyun 	return ret;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun /**
199*4882a593Smuzhiyun  * adxrs450_spi_initial() - use for initializing procedure.
200*4882a593Smuzhiyun  * @st: device instance specific data
201*4882a593Smuzhiyun  * @val: somewhere to pass back the value read
202*4882a593Smuzhiyun  * @chk: Whether to perform fault check
203*4882a593Smuzhiyun  **/
adxrs450_spi_initial(struct adxrs450_state * st,u32 * val,char chk)204*4882a593Smuzhiyun static int adxrs450_spi_initial(struct adxrs450_state *st,
205*4882a593Smuzhiyun 		u32 *val, char chk)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun 	int ret;
208*4882a593Smuzhiyun 	u32 tx;
209*4882a593Smuzhiyun 	struct spi_transfer xfers = {
210*4882a593Smuzhiyun 		.tx_buf = &st->tx,
211*4882a593Smuzhiyun 		.rx_buf = &st->rx,
212*4882a593Smuzhiyun 		.bits_per_word = 8,
213*4882a593Smuzhiyun 		.len = sizeof(st->tx),
214*4882a593Smuzhiyun 	};
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	mutex_lock(&st->buf_lock);
217*4882a593Smuzhiyun 	tx = ADXRS450_SENSOR_DATA;
218*4882a593Smuzhiyun 	if (chk)
219*4882a593Smuzhiyun 		tx |= (ADXRS450_CHK | ADXRS450_P);
220*4882a593Smuzhiyun 	st->tx = cpu_to_be32(tx);
221*4882a593Smuzhiyun 	ret = spi_sync_transfer(st->us, &xfers, 1);
222*4882a593Smuzhiyun 	if (ret) {
223*4882a593Smuzhiyun 		dev_err(&st->us->dev, "Problem while reading initializing data\n");
224*4882a593Smuzhiyun 		goto error_ret;
225*4882a593Smuzhiyun 	}
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	*val = be32_to_cpu(st->rx);
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun error_ret:
230*4882a593Smuzhiyun 	mutex_unlock(&st->buf_lock);
231*4882a593Smuzhiyun 	return ret;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun /* Recommended Startup Sequence by spec */
adxrs450_initial_setup(struct iio_dev * indio_dev)235*4882a593Smuzhiyun static int adxrs450_initial_setup(struct iio_dev *indio_dev)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun 	u32 t;
238*4882a593Smuzhiyun 	u16 data;
239*4882a593Smuzhiyun 	int ret;
240*4882a593Smuzhiyun 	struct adxrs450_state *st = iio_priv(indio_dev);
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	msleep(ADXRS450_STARTUP_DELAY*2);
243*4882a593Smuzhiyun 	ret = adxrs450_spi_initial(st, &t, 1);
244*4882a593Smuzhiyun 	if (ret)
245*4882a593Smuzhiyun 		return ret;
246*4882a593Smuzhiyun 	if (t != 0x01)
247*4882a593Smuzhiyun 		dev_warn(&st->us->dev, "The initial power on response is not correct! Restart without reset?\n");
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	msleep(ADXRS450_STARTUP_DELAY);
250*4882a593Smuzhiyun 	ret = adxrs450_spi_initial(st, &t, 0);
251*4882a593Smuzhiyun 	if (ret)
252*4882a593Smuzhiyun 		return ret;
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	msleep(ADXRS450_STARTUP_DELAY);
255*4882a593Smuzhiyun 	ret = adxrs450_spi_initial(st, &t, 0);
256*4882a593Smuzhiyun 	if (ret)
257*4882a593Smuzhiyun 		return ret;
258*4882a593Smuzhiyun 	if (((t & 0xff) | 0x01) != 0xff || ADXRS450_GET_ST(t) != 2) {
259*4882a593Smuzhiyun 		dev_err(&st->us->dev, "The second response is not correct!\n");
260*4882a593Smuzhiyun 		return -EIO;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	}
263*4882a593Smuzhiyun 	ret = adxrs450_spi_initial(st, &t, 0);
264*4882a593Smuzhiyun 	if (ret)
265*4882a593Smuzhiyun 		return ret;
266*4882a593Smuzhiyun 	if (((t & 0xff) | 0x01) != 0xff || ADXRS450_GET_ST(t) != 2) {
267*4882a593Smuzhiyun 		dev_err(&st->us->dev, "The third response is not correct!\n");
268*4882a593Smuzhiyun 		return -EIO;
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	}
271*4882a593Smuzhiyun 	ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_FAULT1, &data);
272*4882a593Smuzhiyun 	if (ret)
273*4882a593Smuzhiyun 		return ret;
274*4882a593Smuzhiyun 	if (data & 0x0fff) {
275*4882a593Smuzhiyun 		dev_err(&st->us->dev, "The device is not in normal status!\n");
276*4882a593Smuzhiyun 		return -EINVAL;
277*4882a593Smuzhiyun 	}
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	return 0;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun 
adxrs450_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)282*4882a593Smuzhiyun static int adxrs450_write_raw(struct iio_dev *indio_dev,
283*4882a593Smuzhiyun 			      struct iio_chan_spec const *chan,
284*4882a593Smuzhiyun 			      int val,
285*4882a593Smuzhiyun 			      int val2,
286*4882a593Smuzhiyun 			      long mask)
287*4882a593Smuzhiyun {
288*4882a593Smuzhiyun 	int ret;
289*4882a593Smuzhiyun 	switch (mask) {
290*4882a593Smuzhiyun 	case IIO_CHAN_INFO_CALIBBIAS:
291*4882a593Smuzhiyun 		if (val < -0x400 || val >= 0x400)
292*4882a593Smuzhiyun 			return -EINVAL;
293*4882a593Smuzhiyun 		ret = adxrs450_spi_write_reg_16(indio_dev,
294*4882a593Smuzhiyun 						ADXRS450_DNC1, val);
295*4882a593Smuzhiyun 		break;
296*4882a593Smuzhiyun 	default:
297*4882a593Smuzhiyun 		ret = -EINVAL;
298*4882a593Smuzhiyun 		break;
299*4882a593Smuzhiyun 	}
300*4882a593Smuzhiyun 	return ret;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun 
adxrs450_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)303*4882a593Smuzhiyun static int adxrs450_read_raw(struct iio_dev *indio_dev,
304*4882a593Smuzhiyun 			     struct iio_chan_spec const *chan,
305*4882a593Smuzhiyun 			     int *val,
306*4882a593Smuzhiyun 			     int *val2,
307*4882a593Smuzhiyun 			     long mask)
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun 	int ret;
310*4882a593Smuzhiyun 	s16 t;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	switch (mask) {
313*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
314*4882a593Smuzhiyun 		switch (chan->type) {
315*4882a593Smuzhiyun 		case IIO_ANGL_VEL:
316*4882a593Smuzhiyun 			ret = adxrs450_spi_sensor_data(indio_dev, &t);
317*4882a593Smuzhiyun 			if (ret)
318*4882a593Smuzhiyun 				break;
319*4882a593Smuzhiyun 			*val = t;
320*4882a593Smuzhiyun 			ret = IIO_VAL_INT;
321*4882a593Smuzhiyun 			break;
322*4882a593Smuzhiyun 		case IIO_TEMP:
323*4882a593Smuzhiyun 			ret = adxrs450_spi_read_reg_16(indio_dev,
324*4882a593Smuzhiyun 						       ADXRS450_TEMP1, &t);
325*4882a593Smuzhiyun 			if (ret)
326*4882a593Smuzhiyun 				break;
327*4882a593Smuzhiyun 			*val = (t >> 6) + 225;
328*4882a593Smuzhiyun 			ret = IIO_VAL_INT;
329*4882a593Smuzhiyun 			break;
330*4882a593Smuzhiyun 		default:
331*4882a593Smuzhiyun 			ret = -EINVAL;
332*4882a593Smuzhiyun 			break;
333*4882a593Smuzhiyun 		}
334*4882a593Smuzhiyun 		break;
335*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
336*4882a593Smuzhiyun 		switch (chan->type) {
337*4882a593Smuzhiyun 		case IIO_ANGL_VEL:
338*4882a593Smuzhiyun 			*val = 0;
339*4882a593Smuzhiyun 			*val2 = 218166;
340*4882a593Smuzhiyun 			return IIO_VAL_INT_PLUS_NANO;
341*4882a593Smuzhiyun 		case IIO_TEMP:
342*4882a593Smuzhiyun 			*val = 200;
343*4882a593Smuzhiyun 			*val2 = 0;
344*4882a593Smuzhiyun 			return IIO_VAL_INT;
345*4882a593Smuzhiyun 		default:
346*4882a593Smuzhiyun 			return -EINVAL;
347*4882a593Smuzhiyun 		}
348*4882a593Smuzhiyun 	case IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW:
349*4882a593Smuzhiyun 		ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_QUAD1, &t);
350*4882a593Smuzhiyun 		if (ret)
351*4882a593Smuzhiyun 			break;
352*4882a593Smuzhiyun 		*val = t;
353*4882a593Smuzhiyun 		ret = IIO_VAL_INT;
354*4882a593Smuzhiyun 		break;
355*4882a593Smuzhiyun 	case IIO_CHAN_INFO_CALIBBIAS:
356*4882a593Smuzhiyun 		ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_DNC1, &t);
357*4882a593Smuzhiyun 		if (ret)
358*4882a593Smuzhiyun 			break;
359*4882a593Smuzhiyun 		*val = sign_extend32(t, 9);
360*4882a593Smuzhiyun 		ret = IIO_VAL_INT;
361*4882a593Smuzhiyun 		break;
362*4882a593Smuzhiyun 	default:
363*4882a593Smuzhiyun 		ret = -EINVAL;
364*4882a593Smuzhiyun 		break;
365*4882a593Smuzhiyun 	}
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	return ret;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun static const struct iio_chan_spec adxrs450_channels[2][2] = {
371*4882a593Smuzhiyun 	[ID_ADXRS450] = {
372*4882a593Smuzhiyun 		{
373*4882a593Smuzhiyun 			.type = IIO_ANGL_VEL,
374*4882a593Smuzhiyun 			.modified = 1,
375*4882a593Smuzhiyun 			.channel2 = IIO_MOD_Z,
376*4882a593Smuzhiyun 			.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
377*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_CALIBBIAS) |
378*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW) |
379*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_SCALE),
380*4882a593Smuzhiyun 		}, {
381*4882a593Smuzhiyun 			.type = IIO_TEMP,
382*4882a593Smuzhiyun 			.indexed = 1,
383*4882a593Smuzhiyun 			.channel = 0,
384*4882a593Smuzhiyun 			.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
385*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_SCALE),
386*4882a593Smuzhiyun 		}
387*4882a593Smuzhiyun 	},
388*4882a593Smuzhiyun 	[ID_ADXRS453] = {
389*4882a593Smuzhiyun 		{
390*4882a593Smuzhiyun 			.type = IIO_ANGL_VEL,
391*4882a593Smuzhiyun 			.modified = 1,
392*4882a593Smuzhiyun 			.channel2 = IIO_MOD_Z,
393*4882a593Smuzhiyun 			.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
394*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_SCALE) |
395*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW),
396*4882a593Smuzhiyun 		}, {
397*4882a593Smuzhiyun 			.type = IIO_TEMP,
398*4882a593Smuzhiyun 			.indexed = 1,
399*4882a593Smuzhiyun 			.channel = 0,
400*4882a593Smuzhiyun 			.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
401*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_SCALE),
402*4882a593Smuzhiyun 		}
403*4882a593Smuzhiyun 	},
404*4882a593Smuzhiyun };
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun static const struct iio_info adxrs450_info = {
407*4882a593Smuzhiyun 	.read_raw = &adxrs450_read_raw,
408*4882a593Smuzhiyun 	.write_raw = &adxrs450_write_raw,
409*4882a593Smuzhiyun };
410*4882a593Smuzhiyun 
adxrs450_probe(struct spi_device * spi)411*4882a593Smuzhiyun static int adxrs450_probe(struct spi_device *spi)
412*4882a593Smuzhiyun {
413*4882a593Smuzhiyun 	int ret;
414*4882a593Smuzhiyun 	struct adxrs450_state *st;
415*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	/* setup the industrialio driver allocated elements */
418*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
419*4882a593Smuzhiyun 	if (!indio_dev)
420*4882a593Smuzhiyun 		return -ENOMEM;
421*4882a593Smuzhiyun 	st = iio_priv(indio_dev);
422*4882a593Smuzhiyun 	st->us = spi;
423*4882a593Smuzhiyun 	mutex_init(&st->buf_lock);
424*4882a593Smuzhiyun 	/* This is only used for removal purposes */
425*4882a593Smuzhiyun 	spi_set_drvdata(spi, indio_dev);
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	indio_dev->info = &adxrs450_info;
428*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
429*4882a593Smuzhiyun 	indio_dev->channels =
430*4882a593Smuzhiyun 		adxrs450_channels[spi_get_device_id(spi)->driver_data];
431*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(adxrs450_channels);
432*4882a593Smuzhiyun 	indio_dev->name = spi->dev.driver->name;
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	ret = devm_iio_device_register(&spi->dev, indio_dev);
435*4882a593Smuzhiyun 	if (ret)
436*4882a593Smuzhiyun 		return ret;
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	/* Get the device into a sane initial state */
439*4882a593Smuzhiyun 	ret = adxrs450_initial_setup(indio_dev);
440*4882a593Smuzhiyun 	if (ret)
441*4882a593Smuzhiyun 		return ret;
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun 	return 0;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun static const struct spi_device_id adxrs450_id[] = {
447*4882a593Smuzhiyun 	{"adxrs450", ID_ADXRS450},
448*4882a593Smuzhiyun 	{"adxrs453", ID_ADXRS453},
449*4882a593Smuzhiyun 	{}
450*4882a593Smuzhiyun };
451*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, adxrs450_id);
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun static struct spi_driver adxrs450_driver = {
454*4882a593Smuzhiyun 	.driver = {
455*4882a593Smuzhiyun 		.name = "adxrs450",
456*4882a593Smuzhiyun 	},
457*4882a593Smuzhiyun 	.probe = adxrs450_probe,
458*4882a593Smuzhiyun 	.id_table	= adxrs450_id,
459*4882a593Smuzhiyun };
460*4882a593Smuzhiyun module_spi_driver(adxrs450_driver);
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun MODULE_AUTHOR("Cliff Cai <cliff.cai@xxxxxxxxxx>");
463*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices ADXRS450/ADXRS453 Gyroscope SPI driver");
464*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
465