1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 */ 5 6/dts-v1/; 7#include "rv1126.dtsi" 8#include "rv1126-ipc.dtsi" 9#include <dt-bindings/input/input.h> 10 11/ { 12 model = "Rockchip RV1126 38x38 V10 SPI NOR DDR3 Board"; 13 compatible = "rockchip,rv1126-38x38-v10-spi-nor", "rockchip,rv1126"; 14 15 chosen { 16 bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 root=/dev/mtdblock3 rootfstype=squashfs rootwait snd_aloop.index=7"; 17 }; 18 19 /delete-node/ vdd-npu; 20 /delete-node/ vdd-vepu; 21 22 vcc_1v8: vcc-1v8 { 23 compatible = "regulator-fixed"; 24 regulator-name = "vcc_1v8"; 25 regulator-always-on; 26 regulator-boot-on; 27 regulator-min-microvolt = <1800000>; 28 regulator-max-microvolt = <1800000>; 29 }; 30 31 vcc_dvdd: vcc-dvdd { 32 compatible = "regulator-fixed"; 33 regulator-name = "vcc_dvdd"; 34 regulator-always-on; 35 regulator-boot-on; 36 regulator-min-microvolt = <1200000>; 37 regulator-max-microvolt = <1200000>; 38 }; 39 40 vcc3v3_sys: vcc33sys { 41 compatible = "regulator-fixed"; 42 regulator-name = "vcc3v3_sys"; 43 regulator-always-on; 44 regulator-boot-on; 45 regulator-min-microvolt = <3300000>; 46 regulator-max-microvolt = <3300000>; 47 }; 48 49 vcc_sd: vcc-sd { 50 compatible = "regulator-fixed"; 51 gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; 52 pinctrl-0 = <&sdmmc_pwr>; 53 pinctrl-names = "default"; 54 regulator-name = "vcc_sd"; 55 regulator-min-microvolt = <3300000>; 56 regulator-max-microvolt = <3300000>; 57 startup-delay-us = <100000>; 58 vin-supply = <&vcc3v3_sys>; 59 enable-active-high; 60 }; 61 62 vdd_arm: vdd-arm { 63 compatible = "pwm-regulator"; 64 pwms = <&pwm0 0 5000 1>; 65 regulator-name = "vdd_arm"; 66 regulator-min-microvolt = <720000>; 67 regulator-max-microvolt = <1000000>; 68 regulator-init-microvolt = <825000>; 69 regulator-always-on; 70 regulator-boot-on; 71 regulator-settling-time-up-us = <250>; 72 pwm-supply = <&vcc3v3_sys>; 73 status = "okay"; 74 }; 75 76 /* 77 * pwm1 is reserved as voltage adjustment in hardware 78 * use fixed regulator to avoid voltage adjustment by software 79 */ 80 vdd_logic_npu_vepu: vdd-logic-npu-vepu { 81 compatible = "pwm-regulator"; 82 pwms = <&pwm1 0 5000 1>; 83 regulator-name = "vdd_logic_npu_vepu"; 84 regulator-min-microvolt = <720000>; 85 regulator-max-microvolt = <880000>; 86 regulator-init-microvolt = <825000>; 87 regulator-always-on; 88 regulator-boot-on; 89 regulator-settling-time-up-us = <250>; 90 pwm-supply = <&vcc3v3_sys>; 91 status = "okay"; 92 }; 93 94 vdd_logic_npu_vepu_fixed: vdd-logic-npu-vepu-fixed { 95 compatible = "regulator-fixed"; 96 regulator-name = "vdd_logic_npu_vepu-fixed"; 97 regulator-always-on; 98 regulator-boot-on; 99 regulator-min-microvolt = <825000>; 100 regulator-max-microvolt = <825000>; 101 }; 102 103 adc-keys { 104 compatible = "adc-keys"; 105 io-channels = <&saradc 0>; 106 io-channel-names = "buttons"; 107 poll-interval = <100>; 108 keyup-threshold-microvolt = <1800000>; 109 110 esc-key { 111 label = "esc"; 112 linux,code = <KEY_ESC>; 113 press-threshold-microvolt = <0>; 114 }; 115 }; 116 117 cam_ircut0: cam_ircut { 118 status = "okay"; 119 compatible = "rockchip,ircut"; 120 ircut-open-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; 121 ircut-close-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; 122 rockchip,camera-module-index = <1>; 123 rockchip,camera-module-facing = "front"; 124 }; 125 126 flash_ir: flash-ir { 127 status = "okay"; 128 compatible = "led,rgb13h"; 129 label = "pwm-flash-ir"; 130 led-max-microamp = <20000>; 131 flash-max-microamp = <20000>; 132 flash-max-timeout-us = <1000000>; 133 pwms=<&pwm3 0 25000 0>; 134 rockchip,camera-module-index = <1>; 135 rockchip,camera-module-facing = "front"; 136 }; 137 138 i2s0_sound: i2s0-sound { 139 status = "okay"; 140 compatible = "simple-audio-card"; 141 simple-audio-card,format = "i2s"; 142 simple-audio-card,mclk-fs = <256>; 143 simple-audio-card,name = "rockchip,i2s0-sound"; 144 simple-audio-card,cpu { 145 sound-dai = <&i2s0_8ch>; 146 }; 147 simple-audio-card,codec { 148 sound-dai = <&wm8974>; 149 }; 150 }; 151}; 152 153&csi_dphy0 { 154 status = "okay"; 155 156 ports { 157 #address-cells = <1>; 158 #size-cells = <0>; 159 port@0 { 160 reg = <0>; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 164 mipi_in_ucam0: endpoint@1 { 165 reg = <1>; 166 remote-endpoint = <&ucam_out0>; 167 data-lanes = <1 2 3 4>; 168 }; 169 }; 170 port@1 { 171 reg = <1>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 175 csidphy0_out: endpoint@0 { 176 reg = <0>; 177 remote-endpoint = <&mipi_csi2_input>; 178 }; 179 }; 180 }; 181}; 182 183&gmac { 184 phy-mode = "rmii"; 185 clock_in_out = "output"; 186 187 snps,reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; 188 snps,reset-active-low; 189 snps,reset-delays-us = <0 50000 10000>; 190 191 assigned-clocks = <&cru CLK_GMAC_SRC_M0>, <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>; 192 assigned-clock-rates = <0>, <50000000>; 193 assigned-clock-parents = <&cru CLK_GMAC_RGMII_M0>, <&cru CLK_GMAC_SRC_M0>, <&cru RMII_MODE_CLK>; 194 195 pinctrl-names = "default"; 196 pinctrl-0 = <&rmiim0_miim &rgmiim0_rxer &rmiim0_bus2 &rgmiim0_mclkinout>; 197 198 phy-handle = <&phy>; 199 status = "okay"; 200}; 201 202&i2c0 { 203 status = "okay"; 204 205 pcf8563: pcf8563@51 { 206 compatible = "pcf8563"; 207 reg = <0x51>; 208 #clock-cells = <0>; 209 clock-frequency = <32768>; 210 clock-output-names = "xin32k"; 211 }; 212}; 213 214&i2c1 { 215 status = "okay"; 216 clock-frequency = <400000>; 217 218 imx415: imx415@1a { 219 compatible = "sony,imx415"; 220 reg = <0x1a>; 221 clocks = <&cru CLK_MIPICSI_OUT>; 222 clock-names = "xvclk"; 223 power-domains = <&power RV1126_PD_VI>; 224 pinctrl-names = "rockchip,camera_default"; 225 pinctrl-0 = <&mipicsi_clk0>; 226 avdd-supply = <&vcc3v3_sys>; 227 dovdd-supply = <&vcc_1v8>; 228 dvdd-supply = <&vcc_dvdd>; 229 /* reset is always pulled high in v10 */ 230 reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 231 rockchip,camera-module-index = <1>; 232 rockchip,camera-module-facing = "front"; 233 rockchip,camera-module-name = "YT10092"; 234 rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; 235 ir-cut = <&cam_ircut0>; 236 flash-leds = <&flash_ir>; 237 port { 238 ucam_out0: endpoint { 239 remote-endpoint = <&mipi_in_ucam0>; 240 data-lanes = <1 2 3 4>; 241 }; 242 }; 243 }; 244 245}; 246 247&i2c4 { 248 status = "okay"; 249 clock-frequency = <400000>; 250 pinctrl-0 = <&i2c4m1_xfer>; 251 252 wm8974: wm8974@1a { 253 compatible = "wlf,wm8974"; 254 reg = <0x1a>; 255 clocks = <&cru MCLK_I2S0_TX_OUT2IO>; 256 clock-names = "mclk"; 257 pinctrl-names = "default"; 258 assigned-clocks = <&cru MCLK_I2S0_TX_OUT2IO>; 259 assigned-clock-parents = <&cru MCLK_I2S0_TX>; 260 pinctrl-0 = <&i2s0m0_mclk>; 261 #sound-dai-cells = <0>; 262 }; 263}; 264 265&i2s0_8ch { 266 status = "okay"; 267 rockchip,clk-trcm = <1>; 268 #sound-dai-cells = <0>; 269 pinctrl-0 = <&i2s0m0_sclk_tx 270 &i2s0m0_lrck_tx 271 &i2s0m0_sdi0 272 &i2s0m0_sdo0>; 273}; 274 275&isp_reserved { 276 size = <0x20000000>; 277}; 278 279&mdio { 280 phy: phy@1 { 281 compatible = "ethernet-phy-ieee802.3-c22"; 282 reg = <0x1>; 283 }; 284}; 285 286&mipi_csi2 { 287 status = "okay"; 288 289 ports { 290 #address-cells = <1>; 291 #size-cells = <0>; 292 293 port@0 { 294 reg = <0>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 298 mipi_csi2_input: endpoint@1 { 299 reg = <1>; 300 remote-endpoint = <&csidphy0_out>; 301 data-lanes = <1 2 3 4>; 302 }; 303 }; 304 305 port@1 { 306 reg = <1>; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 310 mipi_csi2_output: endpoint@0 { 311 reg = <0>; 312 remote-endpoint = <&cif_mipi_in>; 313 data-lanes = <1 2 3 4>; 314 }; 315 }; 316 }; 317}; 318 319&npu { 320 npu-supply = <&vdd_logic_npu_vepu_fixed>; 321}; 322 323&pinctrl { 324 sdmmc-pwr { 325 /omit-if-no-ref/ 326 sdmmc_pwr: sdmmc-pwr { 327 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 328 }; 329 }; 330}; 331 332&pmu_io_domains { 333 status = "okay"; 334 335 pmuio0-supply = <&vcc3v3_sys>; 336 pmuio1-supply = <&vcc3v3_sys>; 337 vccio2-supply = <&vcc3v3_sys>; 338 vccio4-supply = <&vcc_1v8>; 339 vccio5-supply = <&vcc3v3_sys>; 340 vccio6-supply = <&vcc3v3_sys>; 341 vccio7-supply = <&vcc3v3_sys>; 342}; 343 344&pwm3 { 345 status = "okay"; 346 pinctrl-names = "active"; 347 pinctrl-0 = <&pwm3m0_pins_pull_down>; 348}; 349 350&rkcif { 351 status = "okay"; 352}; 353 354&rkcif_mmu { 355 status = "disabled"; 356}; 357 358&rkcif_mipi_lvds { 359 status = "okay"; 360 361 port { 362 /* MIPI CSI-2 endpoint */ 363 cif_mipi_in: endpoint { 364 remote-endpoint = <&mipi_csi2_output>; 365 data-lanes = <1 2 3 4>; 366 }; 367 }; 368}; 369 370&rkcif_mipi_lvds_sditf { 371 status = "okay"; 372 373 port { 374 /* MIPI CSI-2 endpoint */ 375 mipi_lvds_sditf: endpoint { 376 remote-endpoint = <&isp_in>; 377 data-lanes = <1 2 3 4>; 378 }; 379 }; 380}; 381 382&rkisp_vir0 { 383 status = "okay"; 384 385 ports { 386 port@0 { 387 reg = <0>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 391 isp_in: endpoint@0 { 392 reg = <0>; 393 remote-endpoint = <&mipi_lvds_sditf>; 394 }; 395 }; 396 }; 397}; 398 399&rkvenc { 400 venc-supply = <&vdd_logic_npu_vepu_fixed>; 401}; 402 403&rockchip_suspend { 404 status = "okay"; 405 rockchip,sleep-debug-en = <1>; 406 rockchip,sleep-mode-config = < 407 (0 408 | RKPM_SLP_ARMOFF 409 | RKPM_SLP_PMU_PMUALIVE_32K 410 | RKPM_SLP_PMU_DIS_OSC 411 ) 412 >; 413}; 414 415&saradc { 416 status = "okay"; 417 vref-supply = <&vcc_1v8>; 418}; 419 420&sdmmc0_bus4 { 421 rockchip,pins = 422 /* sdmmc0_d0 */ 423 <1 RK_PA4 1 &pcfg_pull_up_drv_level_0>, 424 /* sdmmc0_d1 */ 425 <1 RK_PA5 1 &pcfg_pull_up_drv_level_0>, 426 /* sdmmc0_d2 */ 427 <1 RK_PA6 1 &pcfg_pull_up_drv_level_0>, 428 /* sdmmc0_d3 */ 429 <1 RK_PA7 1 &pcfg_pull_up_drv_level_0>; 430}; 431 432&sdmmc0_clk { 433 rockchip,pins = 434 /* sdmmc0_clk */ 435 <1 RK_PB0 1 &pcfg_pull_up_drv_level_3>; 436}; 437 438&sdmmc0_cmd { 439 rockchip,pins = 440 /* sdmmc0_cmd */ 441 <1 RK_PB1 1 &pcfg_pull_up_drv_level_0>; 442}; 443 444&sdmmc { 445 bus-width = <4>; 446 cap-mmc-highspeed; 447 cap-sd-highspeed; 448 card-detect-delay = <200>; 449 rockchip,default-sample-phase = <90>; 450 no-sdio; 451 no-mmc; 452 status = "okay"; 453 vmmc-supply = <&vcc_sd>; 454}; 455 456&sfc { 457 status = "okay"; 458 459 flash@0 { 460 compatible = "jedec,spi-nor"; 461 reg = <0>; 462 spi-max-frequency = <100000000>; 463 spi-rx-bus-width = <2>; 464 spi-tx-bus-width = <2>; 465 }; 466}; 467