1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * MAX1241 low-power, 12-bit serial ADC
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX1240-MAX1241.pdf
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
10*4882a593Smuzhiyun #include <linux/iio/iio.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
13*4882a593Smuzhiyun #include <linux/spi/spi.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define MAX1241_VAL_MASK GENMASK(11, 0)
16*4882a593Smuzhiyun #define MAX1241_SHUTDOWN_DELAY_USEC 4
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun enum max1241_id {
19*4882a593Smuzhiyun max1241,
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct max1241 {
23*4882a593Smuzhiyun struct spi_device *spi;
24*4882a593Smuzhiyun struct mutex lock;
25*4882a593Smuzhiyun struct regulator *vdd;
26*4882a593Smuzhiyun struct regulator *vref;
27*4882a593Smuzhiyun struct gpio_desc *shutdown;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun __be16 data ____cacheline_aligned;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static const struct iio_chan_spec max1241_channels[] = {
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun .type = IIO_VOLTAGE,
35*4882a593Smuzhiyun .indexed = 1,
36*4882a593Smuzhiyun .channel = 0,
37*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
38*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE),
39*4882a593Smuzhiyun },
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
max1241_read(struct max1241 * adc)42*4882a593Smuzhiyun static int max1241_read(struct max1241 *adc)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct spi_transfer xfers[] = {
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun * Begin conversion by bringing /CS low for at least
47*4882a593Smuzhiyun * tconv us.
48*4882a593Smuzhiyun */
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun .len = 0,
51*4882a593Smuzhiyun .delay.value = 8,
52*4882a593Smuzhiyun .delay.unit = SPI_DELAY_UNIT_USECS,
53*4882a593Smuzhiyun },
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * Then read two bytes of data in our RX buffer.
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun .rx_buf = &adc->data,
59*4882a593Smuzhiyun .len = 2,
60*4882a593Smuzhiyun },
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return spi_sync_transfer(adc->spi, xfers, ARRAY_SIZE(xfers));
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
max1241_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)66*4882a593Smuzhiyun static int max1241_read_raw(struct iio_dev *indio_dev,
67*4882a593Smuzhiyun struct iio_chan_spec const *chan,
68*4882a593Smuzhiyun int *val, int *val2, long mask)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun int ret, vref_uV;
71*4882a593Smuzhiyun struct max1241 *adc = iio_priv(indio_dev);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun switch (mask) {
74*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
75*4882a593Smuzhiyun mutex_lock(&adc->lock);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (adc->shutdown) {
78*4882a593Smuzhiyun gpiod_set_value(adc->shutdown, 0);
79*4882a593Smuzhiyun udelay(MAX1241_SHUTDOWN_DELAY_USEC);
80*4882a593Smuzhiyun ret = max1241_read(adc);
81*4882a593Smuzhiyun gpiod_set_value(adc->shutdown, 1);
82*4882a593Smuzhiyun } else
83*4882a593Smuzhiyun ret = max1241_read(adc);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun if (ret) {
86*4882a593Smuzhiyun mutex_unlock(&adc->lock);
87*4882a593Smuzhiyun return ret;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun *val = (be16_to_cpu(adc->data) >> 3) & MAX1241_VAL_MASK;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun mutex_unlock(&adc->lock);
93*4882a593Smuzhiyun return IIO_VAL_INT;
94*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
95*4882a593Smuzhiyun vref_uV = regulator_get_voltage(adc->vref);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (vref_uV < 0)
98*4882a593Smuzhiyun return vref_uV;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun *val = vref_uV / 1000;
101*4882a593Smuzhiyun *val2 = 12;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
104*4882a593Smuzhiyun default:
105*4882a593Smuzhiyun return -EINVAL;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun static const struct iio_info max1241_info = {
110*4882a593Smuzhiyun .read_raw = max1241_read_raw,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
max1241_disable_vdd_action(void * data)113*4882a593Smuzhiyun static void max1241_disable_vdd_action(void *data)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct max1241 *adc = data;
116*4882a593Smuzhiyun struct device *dev = &adc->spi->dev;
117*4882a593Smuzhiyun int err;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun err = regulator_disable(adc->vdd);
120*4882a593Smuzhiyun if (err)
121*4882a593Smuzhiyun dev_err(dev, "could not disable vdd regulator.\n");
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
max1241_disable_vref_action(void * data)124*4882a593Smuzhiyun static void max1241_disable_vref_action(void *data)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun struct max1241 *adc = data;
127*4882a593Smuzhiyun struct device *dev = &adc->spi->dev;
128*4882a593Smuzhiyun int err;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun err = regulator_disable(adc->vref);
131*4882a593Smuzhiyun if (err)
132*4882a593Smuzhiyun dev_err(dev, "could not disable vref regulator.\n");
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
max1241_probe(struct spi_device * spi)135*4882a593Smuzhiyun static int max1241_probe(struct spi_device *spi)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun struct device *dev = &spi->dev;
138*4882a593Smuzhiyun struct iio_dev *indio_dev;
139*4882a593Smuzhiyun struct max1241 *adc;
140*4882a593Smuzhiyun int ret;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
143*4882a593Smuzhiyun if (!indio_dev)
144*4882a593Smuzhiyun return -ENOMEM;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun adc = iio_priv(indio_dev);
147*4882a593Smuzhiyun adc->spi = spi;
148*4882a593Smuzhiyun mutex_init(&adc->lock);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun adc->vdd = devm_regulator_get(dev, "vdd");
153*4882a593Smuzhiyun if (IS_ERR(adc->vdd)) {
154*4882a593Smuzhiyun dev_err(dev, "failed to get vdd regulator\n");
155*4882a593Smuzhiyun return PTR_ERR(adc->vdd);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun ret = regulator_enable(adc->vdd);
159*4882a593Smuzhiyun if (ret)
160*4882a593Smuzhiyun return ret;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun ret = devm_add_action_or_reset(dev, max1241_disable_vdd_action, adc);
163*4882a593Smuzhiyun if (ret) {
164*4882a593Smuzhiyun dev_err(dev, "could not set up vdd regulator cleanup action\n");
165*4882a593Smuzhiyun return ret;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun adc->vref = devm_regulator_get(dev, "vref");
169*4882a593Smuzhiyun if (IS_ERR(adc->vref)) {
170*4882a593Smuzhiyun dev_err(dev, "failed to get vref regulator\n");
171*4882a593Smuzhiyun return PTR_ERR(adc->vref);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun ret = regulator_enable(adc->vref);
175*4882a593Smuzhiyun if (ret)
176*4882a593Smuzhiyun return ret;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun ret = devm_add_action_or_reset(dev, max1241_disable_vref_action, adc);
179*4882a593Smuzhiyun if (ret) {
180*4882a593Smuzhiyun dev_err(dev, "could not set up vref regulator cleanup action\n");
181*4882a593Smuzhiyun return ret;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun adc->shutdown = devm_gpiod_get_optional(dev, "shutdown",
185*4882a593Smuzhiyun GPIOD_OUT_HIGH);
186*4882a593Smuzhiyun if (IS_ERR(adc->shutdown))
187*4882a593Smuzhiyun return PTR_ERR(adc->shutdown);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun if (adc->shutdown)
190*4882a593Smuzhiyun dev_dbg(dev, "shutdown pin passed, low-power mode enabled");
191*4882a593Smuzhiyun else
192*4882a593Smuzhiyun dev_dbg(dev, "no shutdown pin passed, low-power mode disabled");
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun indio_dev->name = spi_get_device_id(spi)->name;
195*4882a593Smuzhiyun indio_dev->info = &max1241_info;
196*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
197*4882a593Smuzhiyun indio_dev->channels = max1241_channels;
198*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(max1241_channels);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return devm_iio_device_register(dev, indio_dev);
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun static const struct spi_device_id max1241_id[] = {
204*4882a593Smuzhiyun { "max1241", max1241 },
205*4882a593Smuzhiyun {}
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun static const struct of_device_id max1241_dt_ids[] = {
209*4882a593Smuzhiyun { .compatible = "maxim,max1241" },
210*4882a593Smuzhiyun {}
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max1241_dt_ids);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun static struct spi_driver max1241_spi_driver = {
215*4882a593Smuzhiyun .driver = {
216*4882a593Smuzhiyun .name = "max1241",
217*4882a593Smuzhiyun .of_match_table = max1241_dt_ids,
218*4882a593Smuzhiyun },
219*4882a593Smuzhiyun .probe = max1241_probe,
220*4882a593Smuzhiyun .id_table = max1241_id,
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun module_spi_driver(max1241_spi_driver);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun MODULE_AUTHOR("Alexandru Lazar <alazar@startmail.com>");
225*4882a593Smuzhiyun MODULE_DESCRIPTION("MAX1241 ADC driver");
226*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
227