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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SMI (Smart Multimedia Interface) Common
11 - Yong Wu <yong.wu@mediatek.com>
16 MediaTek SMI have two generations of HW architecture, here is the list
21 There's slight differences between the two SMI, for generation 2, the
23 for generation 1, the register is at smi ao base(smi always on register
24 base). Besides that, the smi async clock should be prepared and enabled for
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/OK3568_Linux_fs/kernel/drivers/memory/
H A Dmtk-smi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
16 #include <soc/mediatek/smi.h>
17 #include <dt-bindings/memory/mt2701-larb-port.h>
18 #include <dt-bindings/memory/mtk-memory-port.h>
37 * or non-security.
52 /* SMI COMMON */
89 struct mtk_smi smi; member
98 static int mtk_smi_clk_enable(const struct mtk_smi *smi) in mtk_smi_clk_enable() argument
102 ret = clk_prepare_enable(smi->clk_apb); in mtk_smi_clk_enable()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iommu/
H A Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
33 SMI Common(Smart Multimedia Interface Common)
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Dsleep34xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Karthik Dasu <karthik-dp@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
57 * with non-Thumb-2-capable firmware.
86 .arch armv7-a
89 stmfd sp!, {r4 - r11, lr} @ save registers on stack
98 smc #1 @ call SMI monitor (smi #1)
103 ldmfd sp!, {r4 - r11, pc}
115 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
121 * - only the minimum set of functions gets copied to internal SRAM at boot
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/OK3568_Linux_fs/kernel/drivers/net/dsa/
H A Drtl8366rb.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
23 #include "realtek-smi-core.h"
315 * struct rtl8366rb - RTL8366RB-specific data
316 * @max_mtu: per-port max MTU setting
358 static int rtl8366rb_get_mib_counter(struct realtek_smi *smi, in rtl8366rb_get_mib_counter() argument
369 mib->offset; in rtl8366rb_get_mib_counter()
374 ret = regmap_write(smi->map, addr, 0); /* Write whatever */ in rtl8366rb_get_mib_counter()
379 ret = regmap_read(smi->map, RTL8366RB_MIB_CTRL_REG, &val); in rtl8366rb_get_mib_counter()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-98dx3236-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
8 - reg: register specifier of MPP registers
18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
45 mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
46 mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
H A Dmarvell,armada-37xx-pinctrl.txt12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
17 common pinctrl bindings used by client devices, including the meaning
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
33 - pins 20-24
34 - functions jtag, gpio
37 - pins 8-10
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H A Dmarvell,armada-39x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
22 mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc)
23 mpp5 5 gpio, ua1(rxd), ua0(cts), smi(mdio)
35 mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio)
38 mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc)
H A Dpinctrl_spear.txt4 - compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
9 - reg : Address range of the pinctrl registers
10 - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
11 - Its values for SPEAr300:
12 - NAND_MODE : <0>
13 - NOR_MODE : <1>
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/OK3568_Linux_fs/u-boot/drivers/mtd/
H A Dst_smi.c5 * SPDX-License-Identifier: GPL-2.0+
8 #include <common.h>
82 * smi_wait_xfer_finish - Wait until TFF is set in status register
92 if (readl(&smicntl->smi_sr) & TFF) in smi_wait_xfer_finish()
99 return -1; in smi_wait_xfer_finish()
103 * smi_read_id - Read flash id
113 writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); in smi_read_id()
114 writel(READ_ID, &smicntl->smi_tr); in smi_read_id()
116 &smicntl->smi_cr2); in smi_read_id()
119 return -EIO; in smi_read_id()
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
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H A Dmt8173.dtsi14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include <dt-bindings/gce/mt8173-gce.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include "mt8173-pinfunc.h"
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/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dcavium.c9 * Copyright (C) 2012-2017 Cavium Inc.
18 #include <linux/dma-direction.h>
19 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
46 * being used. However, non-MMC devices like SD use command and
128 cr = cvm_mmc_cr_types + (cmd->opcode & 0x3f); in cvm_mmc_get_cr_mods()
129 hardware_ctype = cr->ctype; in cvm_mmc_get_cr_mods()
130 hardware_rtype = cr->rtype; in cvm_mmc_get_cr_mods()
131 if (cmd->opcode == MMC_GEN_CMD) in cvm_mmc_get_cr_mods()
132 hardware_ctype = (cmd->arg & 1) ? 1 : 2; in cvm_mmc_get_cr_mods()
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/OK3568_Linux_fs/u-boot/drivers/net/
H A Dmvgbe.c4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 * based on - Driver for MV64360X ethernet ports
12 * SPDX-License-Identifier: GPL-2.0+
15 #include <common.h>
43 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
47 * smi_reg_read - miiphy_read callback function.
55 struct eth_device *dev = eth_get_dev_by_name(bus->name); in smi_reg_read()
57 struct mvgbe_registers *regs = dmvgbe->regs; in smi_reg_read()
65 data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK); in smi_reg_read()
72 return -EFAULT; in smi_reg_read()
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H A Darmada100_fec.c4 * Written-by: Ajay Bhargav <contact@8051projects.net>
10 * SPDX-License-Identifier: GPL-2.0+
13 #include <common.h>
32 struct armdfec_reg *regs = darmdfec->regs; in eth_dump_regs()
35 printf("\noffset: phy_adr, value: 0x%x\n", readl(&regs->phyadr)); in eth_dump_regs()
36 printf("offset: smi, value: 0x%x\n", readl(&regs->smi)); in eth_dump_regs()
49 while (--timeout) { in armdfec_phy_timeout()
64 struct eth_device *dev = eth_get_dev_by_name(bus->name); in smi_reg_read()
66 struct armdfec_reg *regs = darmdfec->regs; in smi_reg_read()
70 val = readl(&regs->phyadr); in smi_reg_read()
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/OK3568_Linux_fs/u-boot/drivers/net/phy/
H A Dmv88e61xx.c11 * SPDX-License-Identifier: GPL-2.0+
33 #include <common.h>
44 #define PORT_MASK ((1 << PORT_COUNT) - 1)
53 /* SMI indirection registers for multichip addressing mode */
222 /* Wait for the current SMI indirect command to complete */
229 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG); in mv88e61xx_smi_wait()
234 } while (--timeout); in mv88e61xx_smi_wait()
236 puts("SMI busy timeout\n"); in mv88e61xx_smi_wait()
237 return -ETIMEDOUT; in mv88e61xx_smi_wait()
241 * The mv88e61xx has three types of addresses: the smi bus address, the device
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H A Dmv88e6352.c5 * SPDX-License-Identifier: GPL-2.0+
8 #include <common.h>
39 /* wait till the SMI is not busy */ in sw_wait_rdy()
48 if (timeout-- == 0) { in sw_wait_rdy()
49 printf("Err..(%s) SMI busy timeout\n", __func__); in sw_wait_rdy()
50 return -EFAULT; in sw_wait_rdy()
139 return -ETIMEDOUT; in ppu_enable()
169 return -ETIMEDOUT; in ppu_disable()
194 /* re-enable the PPU */ in mv88e_sw_program()
231 return -ETIMEDOUT; in mv88e_sw_reset()
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/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/include/mach/
H A Dconfig.h4 * Written-by: Lei Wen <leiwen@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 * It supports common definitions for MVEBU platforms
23 * Set this for the common xor register definitions needed in dram.c
46 #define CONFIG_BUILD_TARGET "u-boot-spl.kwb"
77 #define CONFIG_MII /* expose smi ove miiphy interface */
97 /* Use common timer */
/OK3568_Linux_fs/external/xserver/hw/xwin/
H A DXWin.exe.manifest1 <?xml version="1.0" encoding="UTF-8" standalone="yes"?>
2 <assembly xmlns="urn:schemas-microsoft-com:asm.v1" manifestVersion="1.0">
8 name="Microsoft.Windows.Common-Controls"
16 <asmv3:application xmlns:asmv3="urn:schemas-microsoft-com:asm.v3">
17 <asmv3:windowsSettings xmlns="http://schemas.microsoft.com/SMI/2005/WindowsSettings">
21 <compatibility xmlns="urn:schemas-microsoft-com:compatibility.v1">
23 <!-- Windows Vista -->
24 <supportedOS Id="{e2011457-1546-43c5-a5fe-008deee3d3f0}"/>
25 <!-- Windows 7 -->
26 <supportedOS Id="{35138b9a-5d96-4fbd-8e2d-a2440225f93a}"/>
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/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/spear/
H A Dspl.c7 * SPDX-License-Identifier: GPL-2.0+
10 #include <common.h>
25 clkenb = readl(&misc_p->periph1_clken); in ddr_clock_init()
30 writel(clkenb, &misc_p->periph1_clken); in ddr_clock_init()
31 writel(clkenb, &misc_p->periph1_clken); in ddr_clock_init()
33 ddrpll = readl(&misc_p->pll_ctr_reg); in ddr_clock_init()
44 writel(ddrpll, &misc_p->pll_ctr_reg); in ddr_clock_init()
46 writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN, in ddr_clock_init()
47 &misc_p->periph1_clken); in ddr_clock_init()
91 writel(FREQ_332, &misc_p->pll1_frq); in pll_init()
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/OK3568_Linux_fs/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dconfig.h4 * Written-by: Lei Wen <leiwen@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 * It supports common definitions for Kirkwood platform
80 #define CONFIG_MII /* expose smi ove miiphy interface */
102 /* Needs byte-swapping for ATA data register */
108 /* Each 8-bit ATA register is aligned to a 4-bytes address */
110 /* Controller supports 48-bits LBA addressing */
131 /* Use common timer */
/OK3568_Linux_fs/u-boot/arch/x86/cpu/coreboot/
H A Dcoreboot.c6 * SPDX-License-Identifier: GPL-2.0+
9 #include <common.h>
45 * Un-cache the ROM so the kernel has one in board_final_cleanup()
51 u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1; in board_final_cleanup()
54 /* Make sure this MTRR is the correct Write-Protected type */ in board_final_cleanup()
64 if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) { in board_final_cleanup()
66 * Issue SMI to coreboot to lock down ME and registers in board_final_cleanup()
76 if (gd->flags & GD_FLG_COLD_BOOT) in last_stage_init()
/OK3568_Linux_fs/u-boot/arch/x86/lib/
H A Dacpi_table.c7 * SPDX-License-Identifier: GPL-2.0+
10 #include <common.h>
13 #include <dm/uclass-internal.h>
35 memcpy(rsdp->signature, RSDP_SIG, 8); in acpi_write_rsdp()
36 memcpy(rsdp->oem_id, OEM_ID, 6); in acpi_write_rsdp()
38 rsdp->length = sizeof(struct acpi_rsdp); in acpi_write_rsdp()
39 rsdp->rsdt_address = (u32)rsdt; in acpi_write_rsdp()
49 rsdp->revision = ACPI_RSDP_REV_ACPI_1_0; in acpi_write_rsdp()
51 rsdp->xsdt_address = (u64)(u32)xsdt; in acpi_write_rsdp()
52 rsdp->revision = ACPI_RSDP_REV_ACPI_2_0; in acpi_write_rsdp()
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