1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011 3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 4*4882a593Smuzhiyun * Written-by: Lei Wen <leiwen@marvell.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * This file should be included in board config header file. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * It supports common definitions for MVEBU platforms 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef _MVEBU_CONFIG_H 16*4882a593Smuzhiyun #define _MVEBU_CONFIG_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <asm/arch/soc.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \ 21*4882a593Smuzhiyun || defined(CONFIG_ARMADA_38X) 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * Set this for the common xor register definitions needed in dram.c 24*4882a593Smuzhiyun * for A38x as well here. 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define MV88F78X60 /* for the DDR training bin_hdr code */ 27*4882a593Smuzhiyun #endif 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define CONFIG_SYS_L2_PL310 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 32*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 33*4882a593Smuzhiyun #endif 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * By default kwbimage.cfg from board specific folder is used 37*4882a593Smuzhiyun * If for some board, different configuration file need to be used, 38*4882a593Smuzhiyun * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #ifndef CONFIG_SYS_KWD_CONFIG 41*4882a593Smuzhiyun #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg 42*4882a593Smuzhiyun #endif /* CONFIG_SYS_KWD_CONFIG */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Add target to build it automatically upon "make" */ 45*4882a593Smuzhiyun #ifdef CONFIG_SPL 46*4882a593Smuzhiyun #define CONFIG_BUILD_TARGET "u-boot-spl.kwb" 47*4882a593Smuzhiyun #endif 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* end of 16M scrubbed by training in bootrom */ 50*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000 51*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS_MAX 2 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * SPI Flash configuration 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #ifdef CONFIG_CMD_SF 59*4882a593Smuzhiyun #ifndef CONFIG_ENV_SPI_BUS 60*4882a593Smuzhiyun # define CONFIG_ENV_SPI_BUS 0 61*4882a593Smuzhiyun #endif 62*4882a593Smuzhiyun #ifndef CONFIG_ENV_SPI_CS 63*4882a593Smuzhiyun # define CONFIG_ENV_SPI_CS 0 64*4882a593Smuzhiyun #endif 65*4882a593Smuzhiyun #ifndef CONFIG_ENV_SPI_MAX_HZ 66*4882a593Smuzhiyun # define CONFIG_ENV_SPI_MAX_HZ 50000000 67*4882a593Smuzhiyun #endif 68*4882a593Smuzhiyun #endif 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Needed for SPI NOR booting in SPL */ 71*4882a593Smuzhiyun #define CONFIG_DM_SEQ_ALIAS 1 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * Ethernet Driver configuration 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun #ifdef CONFIG_CMD_NET 77*4882a593Smuzhiyun #define CONFIG_MII /* expose smi ove miiphy interface */ 78*4882a593Smuzhiyun #if !defined(CONFIG_ARMADA_375) 79*4882a593Smuzhiyun #define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */ 80*4882a593Smuzhiyun #endif 81*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 82*4882a593Smuzhiyun #define CONFIG_ARP_TIMEOUT 200 83*4882a593Smuzhiyun #define CONFIG_NET_RETRY_COUNT 50 84*4882a593Smuzhiyun #endif /* CONFIG_CMD_NET */ 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* 87*4882a593Smuzhiyun * I2C related stuff 88*4882a593Smuzhiyun */ 89*4882a593Smuzhiyun #ifdef CONFIG_CMD_I2C 90*4882a593Smuzhiyun #ifndef CONFIG_SYS_I2C_SOFT 91*4882a593Smuzhiyun #define CONFIG_I2C_MVTWSI 92*4882a593Smuzhiyun #endif 93*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SLAVE 0x0 94*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SPEED 100000 95*4882a593Smuzhiyun #endif 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* Use common timer */ 98*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_COUNTS_DOWN 99*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) 100*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_RATE 25000000 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #endif /* __MVEBU_CONFIG_H */ 103