1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011 3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 4*4882a593Smuzhiyun * Written-by: Lei Wen <leiwen@marvell.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * This file should be included in board config header file. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * It supports common definitions for Kirkwood platform 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef _KW_CONFIG_H 16*4882a593Smuzhiyun #define _KW_CONFIG_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #if defined (CONFIG_KW88F6281) 19*4882a593Smuzhiyun #include <asm/arch/kw88f6281.h> 20*4882a593Smuzhiyun #elif defined (CONFIG_KW88F6192) 21*4882a593Smuzhiyun #include <asm/arch/kw88f6192.h> 22*4882a593Smuzhiyun #else 23*4882a593Smuzhiyun #error "SOC Name not defined" 24*4882a593Smuzhiyun #endif /* CONFIG_KW88F6281 */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #include <asm/arch/soc.h> 27*4882a593Smuzhiyun #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ 28*4882a593Smuzhiyun #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ 29*4882a593Smuzhiyun #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * By default kwbimage.cfg from board specific folder is used 33*4882a593Smuzhiyun * If for some board, different configuration file need to be used, 34*4882a593Smuzhiyun * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #ifndef CONFIG_SYS_KWD_CONFIG 37*4882a593Smuzhiyun #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg 38*4882a593Smuzhiyun #endif /* CONFIG_SYS_KWD_CONFIG */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Kirkwood has 2k of Security SRAM, use it for SP */ 41*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 42*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS_MAX 2 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE 45*4882a593Smuzhiyun #define MV_UART_CONSOLE_BASE KW_UART0_BASE 46*4882a593Smuzhiyun #define MV_SATA_BASE KW_SATA_BASE 47*4882a593Smuzhiyun #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET 48*4882a593Smuzhiyun #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* 51*4882a593Smuzhiyun * NAND configuration 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun #ifdef CONFIG_CMD_NAND 54*4882a593Smuzhiyun #define CONFIG_NAND_KIRKWOOD 55*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ 56*4882a593Smuzhiyun #define NAND_ALLOW_ERASE_ALL 1 57*4882a593Smuzhiyun #endif 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * SPI Flash configuration 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun #ifdef CONFIG_CMD_SF 63*4882a593Smuzhiyun #define CONFIG_HARD_SPI 1 64*4882a593Smuzhiyun #ifndef CONFIG_ENV_SPI_BUS 65*4882a593Smuzhiyun # define CONFIG_ENV_SPI_BUS 0 66*4882a593Smuzhiyun #endif 67*4882a593Smuzhiyun #ifndef CONFIG_ENV_SPI_CS 68*4882a593Smuzhiyun # define CONFIG_ENV_SPI_CS 0 69*4882a593Smuzhiyun #endif 70*4882a593Smuzhiyun #ifndef CONFIG_ENV_SPI_MAX_HZ 71*4882a593Smuzhiyun # define CONFIG_ENV_SPI_MAX_HZ 50000000 72*4882a593Smuzhiyun #endif 73*4882a593Smuzhiyun #endif 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * Ethernet Driver configuration 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun #ifdef CONFIG_CMD_NET 79*4882a593Smuzhiyun #define CONFIG_NETCONSOLE /* include NetConsole support */ 80*4882a593Smuzhiyun #define CONFIG_MII /* expose smi ove miiphy interface */ 81*4882a593Smuzhiyun #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ 82*4882a593Smuzhiyun #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 83*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 84*4882a593Smuzhiyun #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 85*4882a593Smuzhiyun #endif /* CONFIG_CMD_NET */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * USB/EHCI 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun #ifdef CONFIG_CMD_USB 91*4882a593Smuzhiyun #define CONFIG_EHCI_IS_TDI 92*4882a593Smuzhiyun #endif /* CONFIG_CMD_USB */ 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* 95*4882a593Smuzhiyun * IDE Support on SATA ports 96*4882a593Smuzhiyun */ 97*4882a593Smuzhiyun #ifdef CONFIG_IDE 98*4882a593Smuzhiyun #define __io 99*4882a593Smuzhiyun #define CONFIG_MVSATA_IDE 100*4882a593Smuzhiyun #define CONFIG_IDE_PREINIT 101*4882a593Smuzhiyun #define CONFIG_MVSATA_IDE_USE_PORT1 102*4882a593Smuzhiyun /* Needs byte-swapping for ATA data register */ 103*4882a593Smuzhiyun #define CONFIG_IDE_SWAP_IO 104*4882a593Smuzhiyun /* Data, registers and alternate blocks are at the same offset */ 105*4882a593Smuzhiyun #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 106*4882a593Smuzhiyun #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 107*4882a593Smuzhiyun #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 108*4882a593Smuzhiyun /* Each 8-bit ATA register is aligned to a 4-bytes address */ 109*4882a593Smuzhiyun #define CONFIG_SYS_ATA_STRIDE 4 110*4882a593Smuzhiyun /* Controller supports 48-bits LBA addressing */ 111*4882a593Smuzhiyun #define CONFIG_LBA48 112*4882a593Smuzhiyun /* CONFIG_IDE requires some #defines for ATA registers */ 113*4882a593Smuzhiyun #define CONFIG_SYS_IDE_MAXBUS 2 114*4882a593Smuzhiyun #define CONFIG_SYS_IDE_MAXDEVICE 2 115*4882a593Smuzhiyun /* ATA registers base is at SATA controller base */ 116*4882a593Smuzhiyun #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE 117*4882a593Smuzhiyun #endif /* CONFIG_IDE */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* 120*4882a593Smuzhiyun * I2C related stuff 121*4882a593Smuzhiyun */ 122*4882a593Smuzhiyun #ifdef CONFIG_CMD_I2C 123*4882a593Smuzhiyun #ifndef CONFIG_SYS_I2C_SOFT 124*4882a593Smuzhiyun #define CONFIG_SYS_I2C 125*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MVTWSI 126*4882a593Smuzhiyun #endif 127*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SLAVE 0x0 128*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SPEED 100000 129*4882a593Smuzhiyun #endif 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* Use common timer */ 132*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_COUNTS_DOWN 133*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) 134*4882a593Smuzhiyun #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #endif /* _KW_CONFIG_H */ 137