Lines Matching +full:smi +full:- +full:common
4 * Written-by: Ajay Bhargav <contact@8051projects.net>
10 * SPDX-License-Identifier: GPL-2.0+
13 #include <common.h>
32 struct armdfec_reg *regs = darmdfec->regs; in eth_dump_regs()
35 printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr)); in eth_dump_regs()
36 printf("offset: smi, value: 0x%x\n", readl(®s->smi)); in eth_dump_regs()
49 while (--timeout) { in armdfec_phy_timeout()
64 struct eth_device *dev = eth_get_dev_by_name(bus->name); in smi_reg_read()
66 struct armdfec_reg *regs = darmdfec->regs; in smi_reg_read()
70 val = readl(®s->phyadr); in smi_reg_read()
79 return -EINVAL; in smi_reg_read()
84 return -EINVAL; in smi_reg_read()
87 /* wait for the SMI register to become available */ in smi_reg_read()
88 if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) { in smi_reg_read()
90 return -1; in smi_reg_read()
93 writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi); in smi_reg_read()
96 if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) { in smi_reg_read()
97 val = readl(®s->smi); in smi_reg_read()
100 return -1; in smi_reg_read()
102 val = readl(®s->smi); in smi_reg_read()
111 struct eth_device *dev = eth_get_dev_by_name(bus->name); in smi_reg_write()
113 struct armdfec_reg *regs = darmdfec->regs; in smi_reg_write()
116 clrsetbits_le32(®s->phyadr, 0x1f, value & 0x1f); in smi_reg_write()
123 return -EINVAL; in smi_reg_write()
127 return -EINVAL; in smi_reg_write()
130 /* wait for the SMI register to become available */ in smi_reg_write()
131 if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) { in smi_reg_write()
133 return -1; in smi_reg_write()
137 ®s->smi); in smi_reg_write()
149 struct armdfec_reg *regs = darmdfec->regs; in abortdma()
154 while (--maxretries) { in abortdma()
155 writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd); in abortdma()
159 while (--delay) { in abortdma()
160 tmp = readl(®s->sdma_cmd); in abortdma()
193 * mach - the 2 most significant bytes of the MAC address.
194 * macl - the 4 least significant bytes of the MAC address.
244 * mach - the 2 most significant bytes of the MAC address.
245 * macl - the 4 least significant bytes of the MAC address.
246 * skip - if 1, skip this address.
247 * rd - the RD field in the address table.
251 * -ENOSPC if table full
282 start = (struct addr_table_entry_t *)(darmdfec->htpr); in add_del_hash_entry()
285 if (!(entry->lo & HTEVALID)) { in add_del_hash_entry()
289 if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8)) in add_del_hash_entry()
290 && (entry->hi == newhi)) in add_del_hash_entry()
299 if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) && in add_del_hash_entry()
300 (entry->hi != newhi) && del) in add_del_hash_entry()
307 return -ENOSPC; in add_del_hash_entry()
317 entry->hi = 0; in add_del_hash_entry()
318 entry->lo = 0; in add_del_hash_entry()
320 entry->hi = newhi; in add_del_hash_entry()
321 entry->lo = newlo; in add_del_hash_entry()
358 struct armdfec_reg *regs = darmdfec->regs; in init_hashtable()
359 memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE); in init_hashtable()
360 writel((u32)darmdfec->htpr, ®s->htpr); in init_hashtable()
364 * This detects PHY chip from address 0-31 by reading PHY status
374 if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0) in ethernet_phy_detect()
383 if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0) in ethernet_phy_detect()
388 if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0) in ethernet_phy_detect()
397 return -1; in ethernet_phy_detect()
406 p_rx_desc = darmdfec->p_rxdesc; in armdfec_init_rx_desc_ring()
408 p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; in armdfec_init_rx_desc_ring()
409 p_rx_desc->buf_size = PKTSIZE_ALIGN; in armdfec_init_rx_desc_ring()
410 p_rx_desc->byte_cnt = 0; in armdfec_init_rx_desc_ring()
411 p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN; in armdfec_init_rx_desc_ring()
412 if (i == (RINGSZ - 1)) { in armdfec_init_rx_desc_ring()
413 p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc; in armdfec_init_rx_desc_ring()
415 p_rx_desc->nxtdesc_p = (struct rx_desc *) in armdfec_init_rx_desc_ring()
417 p_rx_desc = p_rx_desc->nxtdesc_p; in armdfec_init_rx_desc_ring()
420 darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc; in armdfec_init_rx_desc_ring()
426 struct armdfec_reg *regs = darmdfec->regs; in armdfec_init()
433 writel(0, ®s->im); in armdfec_init()
434 writel(0, ®s->ic); in armdfec_init()
436 writel(0, ®s->iwc); in armdfec_init()
453 ®s->sdma_conf); in armdfec_init()
455 writel(PCR_HS, ®s->pconf); /* Hash size is 1/2kb */ in armdfec_init()
462 PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */ in armdfec_init()
463 ®s->pconf_ext); in armdfec_init()
465 update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr); in armdfec_init()
468 temp = (u32)®s->txcdp[TXQ]; in armdfec_init()
469 writel((u32)darmdfec->p_txdesc, temp); in armdfec_init()
470 temp = (u32)®s->rxfdp[RXQ]; in armdfec_init()
471 writel((u32)darmdfec->p_rxdesc, temp); in armdfec_init()
472 temp = (u32)®s->rxcdp[RXQ]; in armdfec_init()
473 writel((u32)darmdfec->p_rxdesc_curr, temp); in armdfec_init()
476 writel(ALL_INTS, ®s->im); in armdfec_init()
479 setbits_le32(®s->pconf, PCR_EN); in armdfec_init()
482 setbits_le32(®s->sdma_cmd, SDMA_CMD_ERD); in armdfec_init()
491 miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR); in armdfec_init()
493 /* Search phy address from range 0-31 */ in armdfec_init()
496 printf("ARMD100 FEC: PHY not detected at address range 0-31\n"); in armdfec_init()
497 return -1; in armdfec_init()
500 miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr); in armdfec_init()
509 miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr); in armdfec_init()
511 if (miiphy_link(dev->name, phy_adr)) in armdfec_init()
516 printf("ARMD100 FEC: No link on %s\n", dev->name); in armdfec_init()
517 return -1; in armdfec_init()
526 struct armdfec_reg *regs = darmdfec->regs; in armdfec_halt()
529 clrbits_le32(®s->sdma_cmd, SDMA_CMD_ERD); in armdfec_halt()
538 writel(0, ®s->im); in armdfec_halt()
539 writel(0, ®s->ic); in armdfec_halt()
540 writel(0, ®s->iwc); in armdfec_halt()
543 clrbits_le32(®s->pconf, PCR_EN); in armdfec_halt()
549 struct armdfec_reg *regs = darmdfec->regs; in armdfec_send()
550 struct tx_desc *p_txdesc = darmdfec->p_txdesc; in armdfec_send()
558 printf("ARMD100 FEC: Non-aligned data too large (%d)\n", in armdfec_send()
560 return -1; in armdfec_send()
562 memcpy(darmdfec->p_aligned_txbuf, p, datasize); in armdfec_send()
563 p = darmdfec->p_aligned_txbuf; in armdfec_send()
566 p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC; in armdfec_send()
567 p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC; in armdfec_send()
568 p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA; in armdfec_send()
569 p_txdesc->cmd_sts |= TX_EN_INT; in armdfec_send()
570 p_txdesc->buf_ptr = p; in armdfec_send()
571 p_txdesc->byte_cnt = datasize; in armdfec_send()
574 temp = (u32)®s->txcdp[TXQ]; in armdfec_send()
576 writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, ®s->sdma_cmd); in armdfec_send()
581 cmd_sts = readl(&p_txdesc->cmd_sts); in armdfec_send()
587 return -1; in armdfec_send()
589 cmd_sts = readl(&p_txdesc->cmd_sts); in armdfec_send()
590 if (!(retry--)) { in armdfec_send()
593 return -1; in armdfec_send()
603 struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr; in armdfec_recv()
614 return -1; in armdfec_recv()
616 } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA); in armdfec_recv()
618 if (p_rxdesc_curr->byte_cnt != 0) { in armdfec_recv()
621 (u32)p_rxdesc_curr->byte_cnt, in armdfec_recv()
622 (u32)p_rxdesc_curr->buf_ptr, in armdfec_recv()
623 (u32)p_rxdesc_curr->cmd_sts); in armdfec_recv()
631 cmd_sts = readl(&p_rxdesc_curr->cmd_sts); in armdfec_recv()
651 p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET, in armdfec_recv()
652 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET)); in armdfec_recv()
657 p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; in armdfec_recv()
658 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; in armdfec_recv()
659 p_rxdesc_curr->byte_cnt = 0; in armdfec_recv()
661 temp = (u32)&darmdfec->p_rxdesc_curr; in armdfec_recv()
662 writel((u32)p_rxdesc_curr->nxtdesc_p, temp); in armdfec_recv()
678 darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE); in armada100_fec_register()
679 if (!darmdfec->htpr) in armada100_fec_register()
682 darmdfec->p_rxdesc = memalign(PKTALIGN, in armada100_fec_register()
685 if (!darmdfec->p_rxdesc) in armada100_fec_register()
688 darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1); in armada100_fec_register()
689 if (!darmdfec->p_rxbuf) in armada100_fec_register()
692 darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); in armada100_fec_register()
693 if (!darmdfec->p_aligned_txbuf) in armada100_fec_register()
696 darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1); in armada100_fec_register()
697 if (!darmdfec->p_txdesc) in armada100_fec_register()
700 dev = &darmdfec->dev; in armada100_fec_register()
702 darmdfec->regs = (void *)base_addr; in armada100_fec_register()
704 /* must be less than sizeof(dev->name) */ in armada100_fec_register()
705 strcpy(dev->name, "armd-fec0"); in armada100_fec_register()
707 dev->init = armdfec_init; in armada100_fec_register()
708 dev->halt = armdfec_halt; in armada100_fec_register()
709 dev->send = armdfec_send; in armada100_fec_register()
710 dev->recv = armdfec_recv; in armada100_fec_register()
718 return -ENOMEM; in armada100_fec_register()
719 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); in armada100_fec_register()
720 mdiodev->read = smi_reg_read; in armada100_fec_register()
721 mdiodev->write = smi_reg_write; in armada100_fec_register()
730 free(darmdfec->p_aligned_txbuf); in armada100_fec_register()
731 free(darmdfec->p_rxbuf); in armada100_fec_register()
732 free(darmdfec->p_rxdesc); in armada100_fec_register()
733 free(darmdfec->htpr); in armada100_fec_register()
737 return -1; in armada100_fec_register()