Lines Matching +full:smi +full:- +full:common
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 * based on - Driver for MV64360X ethernet ports
12 * SPDX-License-Identifier: GPL-2.0+
15 #include <common.h>
43 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
47 * smi_reg_read - miiphy_read callback function.
55 struct eth_device *dev = eth_get_dev_by_name(bus->name); in smi_reg_read()
57 struct mvgbe_registers *regs = dmvgbe->regs; in smi_reg_read()
65 data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK); in smi_reg_read()
72 return -EFAULT; in smi_reg_read()
77 return -EFAULT; in smi_reg_read()
81 /* wait till the SMI is not busy */ in smi_reg_read()
83 /* read smi register */ in smi_reg_read()
85 if (timeout-- == 0) { in smi_reg_read()
86 printf("Err..(%s) SMI busy timeout\n", __func__); in smi_reg_read()
87 return -EFAULT; in smi_reg_read()
96 /* write the smi register */ in smi_reg_read()
103 /* read smi register */ in smi_reg_read()
105 if (timeout-- == 0) { in smi_reg_read()
106 printf("Err..(%s) SMI read ready timeout\n", in smi_reg_read()
108 return -EFAULT; in smi_reg_read()
112 /* Wait for the data to update in the SMI register */ in smi_reg_read()
125 * smi_reg_write - imiiphy_write callback function.
127 * Returns 0 if write succeed, -EINVAL on bad parameters
128 * -ETIME on timeout
133 struct eth_device *dev = eth_get_dev_by_name(bus->name); in smi_reg_write()
135 struct mvgbe_registers *regs = dmvgbe->regs; in smi_reg_write()
142 MVGBE_REG_WR(regs->phyadr, data); in smi_reg_write()
149 return -EINVAL; in smi_reg_write()
153 return -EINVAL; in smi_reg_write()
156 /* wait till the SMI is not busy */ in smi_reg_write()
159 /* read smi register */ in smi_reg_write()
161 if (timeout-- == 0) { in smi_reg_write()
162 printf("Err..(%s) SMI busy timeout\n", __func__); in smi_reg_write()
163 return -ETIME; in smi_reg_write()
173 /* write the smi register */ in smi_reg_write()
204 * set_access_control - Config address decode parameters for Ethernet unit
218 access_prot_reg = MVGBE_REG_RD(regs->epap); in set_access_control()
220 access_prot_reg &= (~(3 << (param->win * 2))); in set_access_control()
221 access_prot_reg |= (param->access_ctrl << (param->win * 2)); in set_access_control()
222 MVGBE_REG_WR(regs->epap, access_prot_reg); in set_access_control()
225 MVGBE_REG_WR(regs->barsz[param->win].size, in set_access_control()
226 (((param->size / 0x10000) - 1) << 16)); in set_access_control()
229 MVGBE_REG_WR(regs->barsz[param->win].bar, in set_access_control()
230 (param->target | param->attrib | param->base_addr)); in set_access_control()
232 if (param->win < 4) in set_access_control()
233 MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr); in set_access_control()
236 if (param->enable == 1) in set_access_control()
237 MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win)); in set_access_control()
239 MVGBE_REG_BITS_SET(regs->bare, (1 << param->win)); in set_access_control()
250 /* Window target - DDR */ in set_dram_access()
256 win_param.base_addr = gd->bd->bi_dram[i].start; in set_dram_access()
257 win_param.size = gd->bd->bi_dram[i].size; in set_dram_access()
289 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
300 MVGBE_REG_WR(regs->dfut[table_index], 0); in port_init_mac_tables()
304 MVGBE_REG_WR(regs->dfsmt[table_index], 0); in port_init_mac_tables()
306 MVGBE_REG_WR(regs->dfomt[table_index], 0); in port_init_mac_tables()
311 * port_uc_addr - This function Set the port unicast address table
344 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); in port_uc_addr()
346 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); in port_uc_addr()
350 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); in port_uc_addr()
353 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); in port_uc_addr()
362 * port_uc_addr_set - This function Set the port Unicast address.
373 MVGBE_REG_WR(regs->macal, mac_l); in port_uc_addr_set()
374 MVGBE_REG_WR(regs->macah, mac_h); in port_uc_addr_set()
381 * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
389 p_rx_desc = dmvgbe->p_rxdesc; in mvgbe_init_rx_desc_ring()
391 p_rx_desc->cmd_sts = in mvgbe_init_rx_desc_ring()
393 p_rx_desc->buf_size = PKTSIZE_ALIGN; in mvgbe_init_rx_desc_ring()
394 p_rx_desc->byte_cnt = 0; in mvgbe_init_rx_desc_ring()
395 p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN; in mvgbe_init_rx_desc_ring()
396 if (i == (RINGSZ - 1)) in mvgbe_init_rx_desc_ring()
397 p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc; in mvgbe_init_rx_desc_ring()
399 p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *) in mvgbe_init_rx_desc_ring()
401 p_rx_desc = p_rx_desc->nxtdesc_p; in mvgbe_init_rx_desc_ring()
404 dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc; in mvgbe_init_rx_desc_ring()
410 struct mvgbe_registers *regs = dmvgbe->regs; in mvgbe_init()
420 MVGBE_REG_WR(regs->ic, 0); in mvgbe_init()
421 MVGBE_REG_WR(regs->ice, 0); in mvgbe_init()
423 MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL); in mvgbe_init()
425 MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT); in mvgbe_init()
429 port_uc_addr_set(regs, dmvgbe->dev.enetaddr); in mvgbe_init()
432 MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL); in mvgbe_init()
433 MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); in mvgbe_init()
434 MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); in mvgbe_init()
437 MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); in mvgbe_init()
438 MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL); in mvgbe_init()
439 MVGBE_REG_WR(regs->tqx[0].tqxtbc, in mvgbe_init()
442 MVGBE_REG_WR(regs->pmtu, 0); in mvgbe_init()
445 MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE in mvgbe_init()
446 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK)); in mvgbe_init()
449 MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN); in mvgbe_init()
452 * Set ethernet MTU for leaky bucket mechanism to 0 - this will in mvgbe_init()
455 MVGBE_REG_WR(regs->pmtu, 0); in mvgbe_init()
458 MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr); in mvgbe_init()
462 MVGBE_REG_WR(regs->rqc, (1 << RXUQ)); in mvgbe_init()
471 miiphy_read(dev->name, MV_PHY_ADR_REQUEST, in mvgbe_init()
474 if (miiphy_link(dev->name, phyadr)) in mvgbe_init()
479 printf("No link on %s\n", dev->name); in mvgbe_init()
480 return -1; in mvgbe_init()
488 struct mvgbe_registers *regs = dmvgbe->regs; in mvgbe_halt()
491 MVGBE_REG_WR(regs->bare, 0x3f); in mvgbe_halt()
493 stop_queue(®s->tqc); in mvgbe_halt()
494 stop_queue(®s->rqc); in mvgbe_halt()
497 MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN); in mvgbe_halt()
499 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4); in mvgbe_halt()
502 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3); in mvgbe_halt()
505 MVGBE_REG_WR(regs->ic, 0); in mvgbe_halt()
506 MVGBE_REG_WR(regs->ice, 0); in mvgbe_halt()
507 MVGBE_REG_WR(regs->pim, 0); in mvgbe_halt()
508 MVGBE_REG_WR(regs->peim, 0); in mvgbe_halt()
516 struct mvgbe_registers *regs = dmvgbe->regs; in mvgbe_write_hwaddr()
519 port_uc_addr_set(regs, dmvgbe->dev.enetaddr); in mvgbe_write_hwaddr()
526 struct mvgbe_registers *regs = dmvgbe->regs; in mvgbe_send()
527 struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc; in mvgbe_send()
535 printf("Non-aligned data too large (%d)\n", in mvgbe_send()
537 return -1; in mvgbe_send()
540 memcpy(dmvgbe->p_aligned_txbuf, p, datasize); in mvgbe_send()
541 p = dmvgbe->p_aligned_txbuf; in mvgbe_send()
544 p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC; in mvgbe_send()
545 p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC; in mvgbe_send()
546 p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA; in mvgbe_send()
547 p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT; in mvgbe_send()
548 p_txdesc->buf_ptr = (u8 *) p; in mvgbe_send()
549 p_txdesc->byte_cnt = datasize; in mvgbe_send()
552 txuq0_reg_addr = (u32)®s->tcqdp[TXUQ]; in mvgbe_send()
559 MVGBE_REG_WR(regs->tqc, (1 << TXUQ)); in mvgbe_send()
564 cmd_sts = readl(&p_txdesc->cmd_sts); in mvgbe_send()
571 return -1; in mvgbe_send()
573 cmd_sts = readl(&p_txdesc->cmd_sts); in mvgbe_send()
581 struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr; in mvgbe_recv()
592 return -1; in mvgbe_recv()
594 } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA); in mvgbe_recv()
596 if (p_rxdesc_curr->byte_cnt != 0) { in mvgbe_recv()
598 __func__, (u32) p_rxdesc_curr->byte_cnt, in mvgbe_recv()
599 (u32) p_rxdesc_curr->buf_ptr, in mvgbe_recv()
600 (u32) p_rxdesc_curr->cmd_sts); in mvgbe_recv()
608 cmd_sts = readl(&p_rxdesc_curr->cmd_sts); in mvgbe_recv()
629 net_process_received_packet((p_rxdesc_curr->buf_ptr + in mvgbe_recv()
631 (int)(p_rxdesc_curr->byte_cnt - in mvgbe_recv()
637 p_rxdesc_curr->cmd_sts = in mvgbe_recv()
639 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; in mvgbe_recv()
640 p_rxdesc_curr->byte_cnt = 0; in mvgbe_recv()
642 rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr; in mvgbe_recv()
643 writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr); in mvgbe_recv()
658 return -ENOMEM; in mvgbe_phylib_init()
660 bus->read = smi_reg_read; in mvgbe_phylib_init()
661 bus->write = smi_reg_write; in mvgbe_phylib_init()
662 strcpy(bus->name, dev->name); in mvgbe_phylib_init()
668 return -ENOMEM; in mvgbe_phylib_init()
677 return -ENODEV; in mvgbe_phylib_init()
706 dmvgbe->p_rxdesc = in mvgbe_initialize()
710 if (!dmvgbe->p_rxdesc) in mvgbe_initialize()
713 dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, in mvgbe_initialize()
716 if (!dmvgbe->p_rxbuf) in mvgbe_initialize()
719 dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); in mvgbe_initialize()
721 if (!dmvgbe->p_aligned_txbuf) in mvgbe_initialize()
724 dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign( in mvgbe_initialize()
727 if (!dmvgbe->p_txdesc) { in mvgbe_initialize()
728 free(dmvgbe->p_aligned_txbuf); in mvgbe_initialize()
730 free(dmvgbe->p_rxbuf); in mvgbe_initialize()
732 free(dmvgbe->p_rxdesc); in mvgbe_initialize()
738 return -1; in mvgbe_initialize()
741 dev = &dmvgbe->dev; in mvgbe_initialize()
743 /* must be less than sizeof(dev->name) */ in mvgbe_initialize()
744 sprintf(dev->name, "egiga%d", devnum); in mvgbe_initialize()
748 dmvgbe->regs = (void *)MVGBE0_BASE; in mvgbe_initialize()
752 dmvgbe->regs = (void *)MVGBE1_BASE; in mvgbe_initialize()
758 return -1; in mvgbe_initialize()
761 dev->init = (void *)mvgbe_init; in mvgbe_initialize()
762 dev->halt = (void *)mvgbe_halt; in mvgbe_initialize()
763 dev->send = (void *)mvgbe_send; in mvgbe_initialize()
764 dev->recv = (void *)mvgbe_recv; in mvgbe_initialize()
765 dev->write_hwaddr = (void *)mvgbe_write_hwaddr; in mvgbe_initialize()
775 return -ENOMEM; in mvgbe_initialize()
776 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); in mvgbe_initialize()
777 mdiodev->read = smi_reg_read; in mvgbe_initialize()
778 mdiodev->write = smi_reg_write; in mvgbe_initialize()
784 miiphy_write(dev->name, MV_PHY_ADR_REQUEST, in mvgbe_initialize()