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/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-a10-pll2.c16 #include <dt-bindings/clock/sun4i-a10-pll2.h>
62 prediv_clk = clk_register_divider(NULL, "pll2-prediv", in sun4i_pll2_setup()
73 /* Setup the gate part of the PLL2 */ in sun4i_pll2_setup()
82 /* Setup the multiplier part of the PLL2 */ in sun4i_pll2_setup()
95 base_clk = clk_register_composite(NULL, "pll2-base", in sun4i_pll2_setup()
109 * PLL2-1x in sun4i_pll2_setup()
130 * PLL2-2x in sun4i_pll2_setup()
133 * a fixed divider from the PLL2 base clock. in sun4i_pll2_setup()
143 /* PLL2-4x */ in sun4i_pll2_setup()
152 /* PLL2-8x */ in sun4i_pll2_setup()
[all …]
/OK3568_Linux_fs/kernel/include/linux/iio/frequency/
H A Dad9523.h126 * @pll2_charge_pump_current_nA: Magnitude of PLL2 charge pump current (nA).
127 * @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
128 * @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
129 * @pll2_freq_doubler_en: PLL2 frequency doubler enable.
130 * @pll2_r2_div: PLL2 R2 divider, range 0..31.
133 * @rpole2: PLL2 loop filter Rpole resistor value.
134 * @rzero: PLL2 loop filter Rzero resistor value.
135 * @cpole1: PLL2 loop filter Cpole capacitor value.
136 * @rzero_bypass_en: PLL2 loop filter Rzero bypass enable.
172 /* PLL2 Setting */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-mod1-clk.yaml44 #include <dt-bindings/clock/sun4i-a10-pll2.h>
50 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
51 <&pll2 SUN4I_A10_PLL2_4X>,
52 <&pll2 SUN4I_A10_PLL2_2X>,
53 <&pll2 SUN4I_A10_PLL2_1X>;
H A Dti,cdce925.txt30 For all PLL1, PLL2, ... an optional child node can be used to specify spread
49 PLL2 {
H A Drenesas,cpg-clocks.yaml76 - const: pll2
202 - const: pll2
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun7i-a20.dtsi50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
217 pll2: clk@01c20008 { label
219 compatible = "allwinner,sun4i-a10-pll2-clk";
222 clock-output-names = "pll2-1x", "pll2-2x",
223 "pll2-4x", "pll2-8x";
530 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
531 <&pll2 SUN4I_A10_PLL2_4X>,
532 <&pll2 SUN4I_A10_PLL2_2X>,
533 <&pll2 SUN4I_A10_PLL2_1X>;
541 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
[all …]
H A Dsun5i-gr8.dtsi45 #include <dt-bindings/clock/sun4i-a10-pll2.h>
115 pll2: clk@01c20008 { label
117 compatible = "allwinner,sun5i-a13-pll2-clk";
120 clock-output-names = "pll2-1x", "pll2-2x",
121 "pll2-4x", "pll2-8x";
387 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
388 <&pll2 SUN4I_A10_PLL2_4X>,
389 <&pll2 SUN4I_A10_PLL2_2X>,
390 <&pll2 SUN4I_A10_PLL2_1X>;
398 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
[all …]
H A Dsun5i.dtsi47 #include <dt-bindings/clock/sun4i-a10-pll2.h>
115 pll2: clk@01c20008 { label
117 compatible = "allwinner,sun5i-a13-pll2-clk";
120 clock-output-names = "pll2-1x", "pll2-2x",
121 "pll2-4x", "pll2-8x";
345 clocks = <&pll2 SUN4I_A10_PLL2_1X>;
H A Dsun4i-a10.dtsi48 #include <dt-bindings/clock/sun4i-a10-pll2.h>
215 pll2: clk@01c20008 { label
217 compatible = "allwinner,sun4i-a10-pll2-clk";
220 clock-output-names = "pll2-1x", "pll2-2x",
221 "pll2-4x", "pll2-8x";
531 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
532 <&pll2 SUN4I_A10_PLL2_4X>,
533 <&pll2 SUN4I_A10_PLL2_2X>,
534 <&pll2 SUN4I_A10_PLL2_1X>;
669 clocks = <&pll2 SUN4I_A10_PLL2_1X>;
/OK3568_Linux_fs/kernel/drivers/mfd/
H A Dsm501.c116 static unsigned long decode_div(unsigned long pll2, unsigned long val, in decode_div() argument
121 pll2 = 288 * MHZ; in decode_div()
123 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
140 unsigned long pll2 = 0; in sm501_dump_clk() local
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
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/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dak4642.c114 #define PLL2 (1 << 6) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
345 pll = PLL2; in ak4642_dai_set_sysclk()
348 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
H A Dadav80x.c207 SND_SOC_DAPM_SUPPLY("PLL2", ADAV80X_PLL_CTRL1, 3, 1, NULL, 0),
223 clk = "PLL2"; in adav80x_dapm_sysclk_check()
270 { "SYSCLK", NULL, "PLL2", adav80x_dapm_sysclk_check },
273 { "PLL2", NULL, "OSC", adav80x_dapm_pll_check },
609 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2"); in adav80x_set_sysclk()
611 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2"); in adav80x_set_sysclk()
809 snd_soc_dapm_force_enable_pin(dapm, "PLL2"); in adav80x_probe()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ in nouveau_hw_decode_pll()
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 = 0; in nouveau_hw_get_pllvals()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/mmp/
H A Dclk-of-mmp2.c108 {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10},
113 …{MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10, 26000000…
128 {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
132 {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
301 static const char * const sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
312 static const char * const disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
319 … * const mmp2_gpu_gc_parent_names[] = {"pll1_2", "pll1_3", "pll2_2", "pll2_3", "pll2", "usb_pll"};
321 static const char * const mmp2_gpu_bus_parent_names[] = {"pll1_4", "pll2", "pll2_2", "usb_pll"};
324 static const char * const mmp3_gpu_gc_parent_names[] = {"pll1", "pll2", "pll1_p", "pll2_p"};
H A Dclk-mmp2.c72 static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
73 static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
115 clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000); in mmp2_clk_init()
116 clk_register_clkdev(clk, "pll2", NULL); in mmp2_clk_init()
150 clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2", in mmp2_clk_init()
166 clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2", in mmp2_clk_init()
/OK3568_Linux_fs/u-boot/drivers/video/tegra124/
H A Dsor.c489 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
510 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
521 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
527 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
565 DUMP_REG(PLL2); in dump_sor_reg()
702 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_enable_dp()
716 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_enable_dp()
726 if (tegra_dc_sor_poll_register(sor, PLL2, in tegra_dc_sor_enable_dp()
734 tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK | in tegra_dc_sor_enable_dp()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
218 pll2 = 0; in setPLL_double_highregs()
227 pll2 |= 0x011f; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c285 u32 *pll1, u32 *pll2) in get_pll_config() argument
294 *pll2 = hibmc_pll_table[i].pll2_config_value; in get_pll_config()
301 *pll2 = CRT_PLL2_HS_25MHZ; in get_pll_config()
317 u32 pll2; /* bit[63:32] of PLL */ in display_ctrl_adjust() local
323 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dsaa711x_regs.h181 /* second PLL (PLL2) and Pulsegenerator Programming */
535 /* second PLL (PLL2) and Pulsegenerator Programming */
541 "Nominal PLL2 DTO"},
543 "PLL2 Increment"},
545 "PLL2 Status"},
558 "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"},
H A Dov7251.c317 { 0x3098, 0x04 }, /* pll2 pre divider */
318 { 0x3099, 0x28 }, /* pll2 multiplier */
319 { 0x309a, 0x05 }, /* pll2 sys divider */
320 { 0x309b, 0x04 }, /* pll2 adc divider */
321 { 0x309d, 0x00 }, /* pll2 divider */
456 { 0x3098, 0x04 }, /* pll2 pre divider */
457 { 0x3099, 0x28 }, /* pll2 multiplier */
458 { 0x309a, 0x05 }, /* pll2 sys divider */
459 { 0x309b, 0x04 }, /* pll2 adc divider */
460 { 0x309d, 0x00 }, /* pll2 divider */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun9i.c30 /* Set up PLL1 (cluster 0) and PLL2 (cluster 1) */ in clock_init_safe()
119 /* Switch cluster 1 to 24MHz clock while changing PLL2 */ in clock_set_pll2()
129 /* Switch cluster 1 back to PLL2 */ in clock_set_pll2()
/OK3568_Linux_fs/kernel/drivers/clk/mxs/
H A Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
231 clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock); in mx28_clocks_init()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun8i_a83t.h19 u32 pll2_cfg; /* 0x08 pll2 audio control */
96 u32 pll2_bias_cfg; /* 0x224 PLL2 audio Bias config */
110 u32 pll2_pattern_cfg0; /* 0x284 PLL2 Pattern register 0 */
115 u32 pll2_pattern_cfg1; /* 0x2a4 PLL2 Pattern register 1 */
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dste-nomadik-stn8815.dtsi196 * that is parent of TIMCLK, PLL1 and PLL2
241 /* PLL2 is usually 864 MHz and divided into a few fixed rates */
242 pll2: pll2@0 { label
253 clocks = <&pll2>;
268 clocks = <&pll2>;
276 clocks = <&pll2>;
/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/
H A Dlowlevel_init.S146 /* Program the PLL2 Divisor Value */
151 /* Program the PLL2 Divisor Value */
156 /* PLL2 DIV2 MMR */
179 /* PLL2 DIV1 MMR */
666 /* PLL2-SYSTEM PLL MMRs */

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