1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ov7251 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 first version
8 */
9
10 //#define DEBUG
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/sysfs.h>
20 #include <linux/slab.h>
21 #include <linux/version.h>
22 #include <linux/rk-camera-module.h>
23 #include <linux/rk-preisp.h>
24 #include <media/media-entity.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-subdev.h>
28 #include <linux/pinctrl/consumer.h>
29
30 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
31
32 #ifndef V4L2_CID_DIGITAL_GAIN
33 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
34 #endif
35
36 #define OV7251_LANES 1
37 #define OV7251_BITS_PER_SAMPLE 10
38 #define OV7251_LINK_FREQ_240 240000000
39
40 #define PIXEL_RATE_WITH_240M_10BIT (OV7251_LINK_FREQ_240 * 2 * \
41 OV7251_LANES / OV7251_BITS_PER_SAMPLE)
42 #define OV7251_XVCLK_FREQ 24000000
43
44 #define CHIP_ID 0x77
45 #define OV7251_REG_CHIP_ID 0x300a
46 #define OV7251_REG_MOD_VENDOR_ID 0x3d10
47 #define OV7251_REG_OPT_LOAD_CTRL 0x3d81
48
49 #define OV7251_REG_CTRL_MODE 0x0100
50 #define OV7251_MODE_SW_STANDBY 0x0
51 #define OV7251_MODE_STREAMING BIT(0)
52
53 #define OV7251_REG_EXPOSURE 0x3500
54 #define OV7251_EXPOSURE_MIN 4
55 #define OV7251_EXPOSURE_STEP 0xf
56 #define OV7251_VTS_MAX 0xffff
57
58 #define OV7251_REG_ANALOG_GAIN 0x350a
59 #define ANALOG_GAIN_MASK 0x3ff
60 #define ANALOG_GAIN_MIN 0x10
61 #define ANALOG_GAIN_MAX 0x3e0
62 #define ANALOG_GAIN_STEP 1
63 #define ANALOG_GAIN_DEFAULT 0x20
64
65 #define OV7251_REG_TEST_PATTERN 0x5e00
66 #define OV7251_TEST_PATTERN_ENABLE 0x80
67 #define OV7251_TEST_PATTERN_DISABLE 0x0
68
69 #define OV7251_REG_VTS 0x380e
70
71 #define OV7251_MIRROR_REG 0x3821
72 #define OV7251_FLIP_REG 0x3820
73
74 #define OV7251_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x01 : VAL & 0xf9)
75 #define OV7251_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x01 : VAL & 0x9f)
76
77 #define REG_DELAY 0xFFFE
78 #define REG_NULL 0xFFFF
79
80 #define OV7251_REG_VALUE_08BIT 1
81 #define OV7251_REG_VALUE_16BIT 2
82 #define OV7251_REG_VALUE_24BIT 3
83
84 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
85 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
86 #define OV7251_NAME "ov7251"
87
88 static const char * const ov7251_supply_names[] = {
89 "avdd", /* Analog power */
90 "dovdd", /* Digital I/O power */
91 "dvdd", /* Digital core power */
92 };
93
94 #define OV7251_NUM_SUPPLIES ARRAY_SIZE(ov7251_supply_names)
95
96 struct regval {
97 u16 addr;
98 u8 val;
99 };
100
101 struct ov7251_mode {
102 u32 bus_fmt;
103 u32 width;
104 u32 height;
105 struct v4l2_fract max_fps;
106 u32 hts_def;
107 u32 vts_def;
108 u32 exp_def;
109 const struct regval *reg_list;
110 u32 hdr_mode;
111 u32 vc[PAD_MAX];
112 };
113
114 struct ov7251 {
115 struct i2c_client *client;
116 struct clk *xvclk;
117 struct gpio_desc *reset_gpio;
118 struct gpio_desc *pwdn_gpio;
119 struct regulator_bulk_data supplies[OV7251_NUM_SUPPLIES];
120
121 struct pinctrl *pinctrl;
122 struct pinctrl_state *pins_default;
123 struct pinctrl_state *pins_sleep;
124
125 struct v4l2_subdev subdev;
126 struct media_pad pad;
127 struct v4l2_ctrl_handler ctrl_handler;
128 struct v4l2_ctrl *exposure;
129 struct v4l2_ctrl *anal_gain;
130 struct v4l2_ctrl *digi_gain;
131 struct v4l2_ctrl *hblank;
132 struct v4l2_ctrl *vblank;
133 struct v4l2_ctrl *test_pattern;
134 struct mutex mutex;
135 bool streaming;
136 bool power_on;
137 const struct ov7251_mode *cur_mode;
138 struct v4l2_fract cur_fps;
139 u32 module_index;
140 const char *module_facing;
141 const char *module_name;
142 const char *len_name;
143 u32 cur_vts;
144 };
145
146 #define to_ov7251(sd) container_of(sd, struct ov7251, subdev)
147
148 /*
149 * Xclk 24Mhz
150 */
151 static const struct regval ov7251_global_regs[] = {
152 {REG_NULL, 0x00},
153 };
154
155
156 static __maybe_unused const struct regval ov7251_640x480_120fps_regs[] = {
157 {0x0103, 0x01},
158 {0x0100, 0x00},
159 {0x3005, 0x00},
160 {0x3012, 0xc0},
161 {0x3013, 0xd2},
162 {0x3014, 0x04},
163 {0x3016, 0x10},
164 {0x3017, 0x00},
165 {0x3018, 0x00},
166 {0x301a, 0x00},
167 {0x301b, 0x00},
168 {0x301c, 0x00},
169 {0x3023, 0x05},
170 {0x3037, 0xf0},
171 {0x3098, 0x04},
172 {0x3099, 0x32},
173 {0x309a, 0x05},
174 {0x309b, 0x04},
175 {0x30b0, 0x0a},
176 {0x30b1, 0x01},
177 {0x30b3, 0x64},
178 {0x30b4, 0x03},
179 {0x30b5, 0x05},
180 {0x3106, 0xda},
181 {0x3500, 0x00},
182 {0x3501, 0x1f},
183 {0x3502, 0x80},
184 {0x3503, 0x07},
185 {0x3509, 0x10},
186 {0x350b, 0x10},
187 {0x3600, 0x1c},
188 {0x3602, 0x62},
189 {0x3620, 0xb7},
190 {0x3622, 0x04},
191 {0x3626, 0x21},
192 {0x3627, 0x30},
193 {0x3630, 0x44},
194 {0x3631, 0x35},
195 {0x3634, 0x60},
196 {0x3636, 0x00},
197 {0x3662, 0x01},
198 {0x3663, 0x70},
199 {0x3664, 0xf0},
200 {0x3666, 0x0a},
201 {0x3669, 0x1a},
202 {0x366a, 0x00},
203 {0x366b, 0x50},
204 {0x3673, 0x01},
205 {0x3674, 0xef},
206 {0x3675, 0x03},
207 {0x3705, 0xc1},
208 {0x3709, 0x40},
209 {0x373c, 0x08},
210 {0x3742, 0x00},
211 {0x3757, 0xb3},
212 {0x3788, 0x00},
213 {0x37a8, 0x01},
214 {0x37a9, 0xc0},
215 {0x3800, 0x00},
216 {0x3801, 0x04},
217 {0x3802, 0x00},
218 {0x3803, 0x04},
219 {0x3804, 0x02},
220 {0x3805, 0x8b},
221 {0x3806, 0x01},
222 {0x3807, 0xeb},
223 {0x3808, 0x02},
224 {0x3809, 0x80},
225 {0x380a, 0x01},
226 {0x380b, 0xe0},
227 {0x380c, 0x03},
228 {0x380d, 0xa1},
229 {0x380e, 0x02},
230 {0x380f, 0x1a},
231 {0x3810, 0x00},
232 {0x3811, 0x04},
233 {0x3812, 0x00},
234 {0x3813, 0x05},
235 {0x3814, 0x11},
236 {0x3815, 0x11},
237 {0x3820, 0x40},
238 {0x3821, 0x00},
239 {0x382f, 0x0e},
240 {0x3832, 0x00},
241 {0x3833, 0x05},
242 {0x3834, 0x00},
243 {0x3835, 0x0c},
244 {0x3837, 0x00},
245 {0x3b80, 0x00},
246 {0x3b81, 0xa5},
247 {0x3b82, 0x10},
248 {0x3b83, 0x00},
249 {0x3b84, 0x08},
250 {0x3b85, 0x00},
251 {0x3b86, 0x01},
252 {0x3b87, 0x00},
253 {0x3b88, 0x00},
254 {0x3b89, 0x00},
255 {0x3b8a, 0x00},
256 {0x3b8b, 0x05},
257 {0x3b8c, 0x00},
258 {0x3b8d, 0x00},
259 {0x3b8e, 0x00},
260 {0x3b8f, 0x1a},
261 {0x3b94, 0x05},
262 {0x3b95, 0xf2},
263 {0x3b96, 0x40},
264 {0x3c00, 0x89},
265 {0x3c01, 0x63},
266 {0x3c02, 0x01},
267 {0x3c03, 0x00},
268 {0x3c04, 0x00},
269 {0x3c05, 0x03},
270 {0x3c06, 0x00},
271 {0x3c07, 0x06},
272 {0x3c0c, 0x01},
273 {0x3c0d, 0xd0},
274 {0x3c0e, 0x02},
275 {0x3c0f, 0x0a},
276 {0x4001, 0x42},
277 {0x4004, 0x04},
278 {0x4005, 0x00},
279 {0x404e, 0x01},
280 {0x4300, 0xff},
281 {0x4301, 0x00},
282 {0x4501, 0x48},
283 {0x4600, 0x00},
284 {0x4601, 0x4e},
285 {0x4801, 0x0f},
286 {0x4806, 0x0f},
287 {0x4819, 0xaa},
288 {0x4823, 0x3e},
289 {0x4837, 0x19},
290 {0x4a0d, 0x00},
291 {0x4a47, 0x7f},
292 {0x4a49, 0xf0},
293 {0x4a4b, 0x30},
294 {0x5000, 0x85},
295 {0x5001, 0x80},
296 {REG_NULL, 0x00},
297 };
298
299 /*
300 * Xclk 24Mhz
301 * max_framerate 30fps
302 * mipi_datarate per lane 630Mbps, 2lane
303 */
304 static __maybe_unused const struct regval ov7251_setting_vga_30fps[] = {
305 { 0x3005, 0x00 },
306 { 0x3012, 0xc0 },
307 { 0x3013, 0xd2 },
308 { 0x3014, 0x04 },
309 { 0x3016, 0xf0 },
310 { 0x3017, 0xf0 },
311 { 0x3018, 0xf0 },
312 { 0x301a, 0xf0 },
313 { 0x301b, 0xf0 },
314 { 0x301c, 0xf0 },
315 { 0x3023, 0x05 },
316 { 0x3037, 0xf0 },
317 { 0x3098, 0x04 }, /* pll2 pre divider */
318 { 0x3099, 0x28 }, /* pll2 multiplier */
319 { 0x309a, 0x05 }, /* pll2 sys divider */
320 { 0x309b, 0x04 }, /* pll2 adc divider */
321 { 0x309d, 0x00 }, /* pll2 divider */
322 { 0x30b0, 0x0a }, /* pll1 pix divider */
323 { 0x30b1, 0x01 }, /* pll1 divider */
324 { 0x30b3, 0x64 }, /* pll1 multiplier */
325 { 0x30b4, 0x03 }, /* pll1 pre divider */
326 { 0x30b5, 0x05 }, /* pll1 mipi divider */
327 { 0x3106, 0xda },
328 { 0x3503, 0x07 },
329 { 0x3509, 0x10 },
330 { 0x3600, 0x1c },
331 { 0x3602, 0x62 },
332 { 0x3620, 0xb7 },
333 { 0x3622, 0x04 },
334 { 0x3626, 0x21 },
335 { 0x3627, 0x30 },
336 { 0x3630, 0x44 },
337 { 0x3631, 0x35 },
338 { 0x3634, 0x60 },
339 { 0x3636, 0x00 },
340 { 0x3662, 0x01 },
341 { 0x3663, 0x70 },
342 { 0x3664, 0x50 },
343 { 0x3666, 0x0a },
344 { 0x3669, 0x1a },
345 { 0x366a, 0x00 },
346 { 0x366b, 0x50 },
347 { 0x3673, 0x01 },
348 { 0x3674, 0xff },
349 { 0x3675, 0x03 },
350 { 0x3705, 0xc1 },
351 { 0x3709, 0x40 },
352 { 0x373c, 0x08 },
353 { 0x3742, 0x00 },
354 { 0x3757, 0xb3 },
355 { 0x3788, 0x00 },
356 { 0x37a8, 0x01 },
357 { 0x37a9, 0xc0 },
358 { 0x3800, 0x00 },
359 { 0x3801, 0x04 },
360 { 0x3802, 0x00 },
361 { 0x3803, 0x04 },
362 { 0x3804, 0x02 },
363 { 0x3805, 0x8b },
364 { 0x3806, 0x01 },
365 { 0x3807, 0xeb },
366 { 0x3808, 0x02 }, /* width high */
367 { 0x3809, 0x80 }, /* width low */
368 { 0x380a, 0x01 }, /* height high */
369 { 0x380b, 0xe0 }, /* height low */
370 { 0x380c, 0x03 }, /* total horiz timing high */
371 { 0x380d, 0xa0 }, /* total horiz timing low */
372 { 0x380e, 0x06 }, /* total vertical timing high */
373 { 0x380f, 0xbc }, /* total vertical timing low */
374 { 0x3810, 0x00 },
375 { 0x3811, 0x04 },
376 { 0x3812, 0x00 },
377 { 0x3813, 0x05 },
378 { 0x3814, 0x11 },
379 { 0x3815, 0x11 },
380 { 0x3820, 0x40 },
381 { 0x3821, 0x00 },
382 { 0x382f, 0x0e },
383 { 0x3832, 0x00 },
384 { 0x3833, 0x05 },
385 { 0x3834, 0x00 },
386 { 0x3835, 0x0c },
387 { 0x3837, 0x00 },
388 { 0x3b80, 0x00 },
389 { 0x3b81, 0xa5 },
390 { 0x3b82, 0x10 },
391 { 0x3b83, 0x00 },
392 { 0x3b84, 0x08 },
393 { 0x3b85, 0x00 },
394 { 0x3b86, 0x01 },
395 { 0x3b87, 0x00 },
396 { 0x3b88, 0x00 },
397 { 0x3b89, 0x00 },
398 { 0x3b8a, 0x00 },
399 { 0x3b8b, 0x05 },
400 { 0x3b8c, 0x00 },
401 { 0x3b8d, 0x00 },
402 { 0x3b8e, 0x00 },
403 { 0x3b8f, 0x1a },
404 { 0x3b94, 0x05 },
405 { 0x3b95, 0xf2 },
406 { 0x3b96, 0x40 },
407 { 0x3c00, 0x89 },
408 { 0x3c01, 0x63 },
409 { 0x3c02, 0x01 },
410 { 0x3c03, 0x00 },
411 { 0x3c04, 0x00 },
412 { 0x3c05, 0x03 },
413 { 0x3c06, 0x00 },
414 { 0x3c07, 0x06 },
415 { 0x3c0c, 0x01 },
416 { 0x3c0d, 0xd0 },
417 { 0x3c0e, 0x02 },
418 { 0x3c0f, 0x0a },
419 { 0x4001, 0x42 },
420 { 0x4004, 0x04 },
421 { 0x4005, 0x00 },
422 { 0x404e, 0x01 },
423 { 0x4300, 0xff },
424 { 0x4301, 0x00 },
425 { 0x4315, 0x00 },
426 { 0x4501, 0x48 },
427 { 0x4600, 0x00 },
428 { 0x4601, 0x4e },
429 { 0x4801, 0x0f },
430 { 0x4806, 0x0f },
431 { 0x4819, 0xaa },
432 { 0x4823, 0x3e },
433 { 0x4837, 0x19 },
434 { 0x4a0d, 0x00 },
435 { 0x4a47, 0x7f },
436 { 0x4a49, 0xf0 },
437 { 0x4a4b, 0x30 },
438 { 0x5000, 0x85 },
439 { 0x5001, 0x80 },
440 {REG_NULL, 0x00 },
441 };
442
443 static __maybe_unused const struct regval ov7251_setting_vga_60fps[] = {
444 { 0x3005, 0x00 },
445 { 0x3012, 0xc0 },
446 { 0x3013, 0xd2 },
447 { 0x3014, 0x04 },
448 { 0x3016, 0x10 },
449 { 0x3017, 0x00 },
450 { 0x3018, 0x00 },
451 { 0x301a, 0x00 },
452 { 0x301b, 0x00 },
453 { 0x301c, 0x00 },
454 { 0x3023, 0x05 },
455 { 0x3037, 0xf0 },
456 { 0x3098, 0x04 }, /* pll2 pre divider */
457 { 0x3099, 0x28 }, /* pll2 multiplier */
458 { 0x309a, 0x05 }, /* pll2 sys divider */
459 { 0x309b, 0x04 }, /* pll2 adc divider */
460 { 0x309d, 0x00 }, /* pll2 divider */
461 { 0x30b0, 0x0a }, /* pll1 pix divider */
462 { 0x30b1, 0x01 }, /* pll1 divider */
463 { 0x30b3, 0x64 }, /* pll1 multiplier */
464 { 0x30b4, 0x03 }, /* pll1 pre divider */
465 { 0x30b5, 0x05 }, /* pll1 mipi divider */
466 { 0x3106, 0xda },
467 { 0x3503, 0x07 },
468 { 0x3509, 0x10 },
469 { 0x3600, 0x1c },
470 { 0x3602, 0x62 },
471 { 0x3620, 0xb7 },
472 { 0x3622, 0x04 },
473 { 0x3626, 0x21 },
474 { 0x3627, 0x30 },
475 { 0x3630, 0x44 },
476 { 0x3631, 0x35 },
477 { 0x3634, 0x60 },
478 { 0x3636, 0x00 },
479 { 0x3662, 0x01 },
480 { 0x3663, 0x70 },
481 { 0x3664, 0x50 },
482 { 0x3666, 0x0a },
483 { 0x3669, 0x1a },
484 { 0x366a, 0x00 },
485 { 0x366b, 0x50 },
486 { 0x3673, 0x01 },
487 { 0x3674, 0xff },
488 { 0x3675, 0x03 },
489 { 0x3705, 0xc1 },
490 { 0x3709, 0x40 },
491 { 0x373c, 0x08 },
492 { 0x3742, 0x00 },
493 { 0x3757, 0xb3 },
494 { 0x3788, 0x00 },
495 { 0x37a8, 0x01 },
496 { 0x37a9, 0xc0 },
497 { 0x3800, 0x00 },
498 { 0x3801, 0x04 },
499 { 0x3802, 0x00 },
500 { 0x3803, 0x04 },
501 { 0x3804, 0x02 },
502 { 0x3805, 0x8b },
503 { 0x3806, 0x01 },
504 { 0x3807, 0xeb },
505 { 0x3808, 0x02 }, /* width high */
506 { 0x3809, 0x80 }, /* width low */
507 { 0x380a, 0x01 }, /* height high */
508 { 0x380b, 0xe0 }, /* height low */
509 { 0x380c, 0x03 }, /* total horiz timing high */
510 { 0x380d, 0xa0 }, /* total horiz timing low */
511 { 0x380e, 0x03 }, /* total vertical timing high */
512 { 0x380f, 0x5c }, /* total vertical timing low */
513 { 0x3810, 0x00 },
514 { 0x3811, 0x04 },
515 { 0x3812, 0x00 },
516 { 0x3813, 0x05 },
517 { 0x3814, 0x11 },
518 { 0x3815, 0x11 },
519 { 0x3820, 0x40 },
520 { 0x3821, 0x00 },
521 { 0x382f, 0x0e },
522 { 0x3832, 0x00 },
523 { 0x3833, 0x05 },
524 { 0x3834, 0x00 },
525 { 0x3835, 0x0c },
526 { 0x3837, 0x00 },
527 { 0x3b80, 0x00 },
528 { 0x3b81, 0xa5 },
529 { 0x3b82, 0x10 },
530 { 0x3b83, 0x00 },
531 { 0x3b84, 0x08 },
532 { 0x3b85, 0x00 },
533 { 0x3b86, 0x01 },
534 { 0x3b87, 0x00 },
535 { 0x3b88, 0x00 },
536 { 0x3b89, 0x00 },
537 { 0x3b8a, 0x00 },
538 { 0x3b8b, 0x05 },
539 { 0x3b8c, 0x00 },
540 { 0x3b8d, 0x00 },
541 { 0x3b8e, 0x00 },
542 { 0x3b8f, 0x1a },
543 { 0x3b94, 0x05 },
544 { 0x3b95, 0xf2 },
545 { 0x3b96, 0x40 },
546 { 0x3c00, 0x89 },
547 { 0x3c01, 0x63 },
548 { 0x3c02, 0x01 },
549 { 0x3c03, 0x00 },
550 { 0x3c04, 0x00 },
551 { 0x3c05, 0x03 },
552 { 0x3c06, 0x00 },
553 { 0x3c07, 0x06 },
554 { 0x3c0c, 0x01 },
555 { 0x3c0d, 0xd0 },
556 { 0x3c0e, 0x02 },
557 { 0x3c0f, 0x0a },
558 { 0x4001, 0x42 },
559 { 0x4004, 0x04 },
560 { 0x4005, 0x00 },
561 { 0x404e, 0x01 },
562 { 0x4300, 0xff },
563 { 0x4301, 0x00 },
564 { 0x4315, 0x00 },
565 { 0x4501, 0x48 },
566 { 0x4600, 0x00 },
567 { 0x4601, 0x4e },
568 { 0x4801, 0x0f },
569 { 0x4806, 0x0f },
570 { 0x4819, 0xaa },
571 { 0x4823, 0x3e },
572 { 0x4837, 0x19 },
573 { 0x4a0d, 0x00 },
574 { 0x4a47, 0x7f },
575 { 0x4a49, 0xf0 },
576 { 0x4a4b, 0x30 },
577 { 0x5000, 0x85 },
578 { 0x5001, 0x80 },
579 {REG_NULL, 0x00 },
580 };
581
582 static __maybe_unused const struct regval ov7251_setting_vga_90fps[] = {
583 { 0x3005, 0x00 },
584 { 0x3012, 0xc0 },
585 { 0x3013, 0xd2 },
586 { 0x3014, 0x04 },
587 { 0x3016, 0x10 },
588 { 0x3017, 0x00 },
589 { 0x3018, 0x00 },
590 { 0x301a, 0x00 },
591 { 0x301b, 0x00 },
592 { 0x301c, 0x00 },
593 { 0x3023, 0x05 },
594 { 0x3037, 0xf0 },
595 { 0x3098, 0x04 }, /* pll2 pre divider */
596 { 0x3099, 0x28 }, /* pll2 multiplier */
597 { 0x309a, 0x05 }, /* pll2 sys divider */
598 { 0x309b, 0x04 }, /* pll2 adc divider */
599 { 0x309d, 0x00 }, /* pll2 divider */
600 { 0x30b0, 0x0a }, /* pll1 pix divider */
601 { 0x30b1, 0x01 }, /* pll1 divider */
602 { 0x30b3, 0x64 }, /* pll1 multiplier */
603 { 0x30b4, 0x03 }, /* pll1 pre divider */
604 { 0x30b5, 0x05 }, /* pll1 mipi divider */
605 { 0x3106, 0xda },
606 { 0x3503, 0x07 },
607 { 0x3509, 0x10 },
608 { 0x3600, 0x1c },
609 { 0x3602, 0x62 },
610 { 0x3620, 0xb7 },
611 { 0x3622, 0x04 },
612 { 0x3626, 0x21 },
613 { 0x3627, 0x30 },
614 { 0x3630, 0x44 },
615 { 0x3631, 0x35 },
616 { 0x3634, 0x60 },
617 { 0x3636, 0x00 },
618 { 0x3662, 0x01 },
619 { 0x3663, 0x70 },
620 { 0x3664, 0x50 },
621 { 0x3666, 0x0a },
622 { 0x3669, 0x1a },
623 { 0x366a, 0x00 },
624 { 0x366b, 0x50 },
625 { 0x3673, 0x01 },
626 { 0x3674, 0xff },
627 { 0x3675, 0x03 },
628 { 0x3705, 0xc1 },
629 { 0x3709, 0x40 },
630 { 0x373c, 0x08 },
631 { 0x3742, 0x00 },
632 { 0x3757, 0xb3 },
633 { 0x3788, 0x00 },
634 { 0x37a8, 0x01 },
635 { 0x37a9, 0xc0 },
636 { 0x3800, 0x00 },
637 { 0x3801, 0x04 },
638 { 0x3802, 0x00 },
639 { 0x3803, 0x04 },
640 { 0x3804, 0x02 },
641 { 0x3805, 0x8b },
642 { 0x3806, 0x01 },
643 { 0x3807, 0xeb },
644 { 0x3808, 0x02 }, /* width high */
645 { 0x3809, 0x80 }, /* width low */
646 { 0x380a, 0x01 }, /* height high */
647 { 0x380b, 0xe0 }, /* height low */
648 { 0x380c, 0x03 }, /* total horiz timing high */
649 { 0x380d, 0xa0 }, /* total horiz timing low */
650 { 0x380e, 0x02 }, /* total vertical timing high */
651 { 0x380f, 0x3c }, /* total vertical timing low */
652 { 0x3810, 0x00 },
653 { 0x3811, 0x04 },
654 { 0x3812, 0x00 },
655 { 0x3813, 0x05 },
656 { 0x3814, 0x11 },
657 { 0x3815, 0x11 },
658 { 0x3820, 0x40 },
659 { 0x3821, 0x00 },
660 { 0x382f, 0x0e },
661 { 0x3832, 0x00 },
662 { 0x3833, 0x05 },
663 { 0x3834, 0x00 },
664 { 0x3835, 0x0c },
665 { 0x3837, 0x00 },
666 { 0x3b80, 0x00 },
667 { 0x3b81, 0xa5 },
668 { 0x3b82, 0x10 },
669 { 0x3b83, 0x00 },
670 { 0x3b84, 0x08 },
671 { 0x3b85, 0x00 },
672 { 0x3b86, 0x01 },
673 { 0x3b87, 0x00 },
674 { 0x3b88, 0x00 },
675 { 0x3b89, 0x00 },
676 { 0x3b8a, 0x00 },
677 { 0x3b8b, 0x05 },
678 { 0x3b8c, 0x00 },
679 { 0x3b8d, 0x00 },
680 { 0x3b8e, 0x00 },
681 { 0x3b8f, 0x1a },
682 { 0x3b94, 0x05 },
683 { 0x3b95, 0xf2 },
684 { 0x3b96, 0x40 },
685 { 0x3c00, 0x89 },
686 { 0x3c01, 0x63 },
687 { 0x3c02, 0x01 },
688 { 0x3c03, 0x00 },
689 { 0x3c04, 0x00 },
690 { 0x3c05, 0x03 },
691 { 0x3c06, 0x00 },
692 { 0x3c07, 0x06 },
693 { 0x3c0c, 0x01 },
694 { 0x3c0d, 0xd0 },
695 { 0x3c0e, 0x02 },
696 { 0x3c0f, 0x0a },
697 { 0x4001, 0x42 },
698 { 0x4004, 0x04 },
699 { 0x4005, 0x00 },
700 { 0x404e, 0x01 },
701 { 0x4300, 0xff },
702 { 0x4301, 0x00 },
703 { 0x4315, 0x00 },
704 { 0x4501, 0x48 },
705 { 0x4600, 0x00 },
706 { 0x4601, 0x4e },
707 { 0x4801, 0x0f },
708 { 0x4806, 0x0f },
709 { 0x4819, 0xaa },
710 { 0x4823, 0x3e },
711 { 0x4837, 0x19 },
712 { 0x4a0d, 0x00 },
713 { 0x4a47, 0x7f },
714 { 0x4a49, 0xf0 },
715 { 0x4a4b, 0x30 },
716 { 0x5000, 0x85 },
717 { 0x5001, 0x80 },
718 {REG_NULL, 0x00 },
719 };
720
721 static const struct ov7251_mode supported_modes[] = {
722 {
723 .width = 640,
724 .height = 480,
725 .max_fps = {
726 .numerator = 10000,
727 .denominator = 1200000,
728 },
729 .exp_def = 0x00f8,
730 .hts_def = 0x03a1,
731 .vts_def = 0x021a,
732 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
733 .reg_list = ov7251_640x480_120fps_regs,
734 .hdr_mode = NO_HDR,
735 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
736 }
737 };
738
739 static const s64 link_freq_menu_items[] = {
740 OV7251_LINK_FREQ_240
741 };
742
743 static const char * const ov7251_test_pattern_menu[] = {
744 "Disabled",
745 "Vertical Color Bar Type 1",
746 "Vertical Color Bar Type 2",
747 "Vertical Color Bar Type 3",
748 "Vertical Color Bar Type 4"
749 };
750
751 /* Write registers up to 4 at a time */
ov7251_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)752 static int ov7251_write_reg(struct i2c_client *client, u16 reg,
753 u32 len, u32 val)
754 {
755 u32 buf_i, val_i;
756 u8 buf[6];
757 u8 *val_p;
758 __be32 val_be;
759
760 if (len > 4)
761 return -EINVAL;
762
763 buf[0] = reg >> 8;
764 buf[1] = reg & 0xff;
765
766 val_be = cpu_to_be32(val);
767 val_p = (u8 *)&val_be;
768 buf_i = 2;
769 val_i = 4 - len;
770
771 while (val_i < 4)
772 buf[buf_i++] = val_p[val_i++];
773
774 if (i2c_master_send(client, buf, len + 2) != len + 2)
775 return -EIO;
776 return 0;
777 }
778
ov7251_write_array(struct i2c_client * client,const struct regval * regs)779 static int ov7251_write_array(struct i2c_client *client,
780 const struct regval *regs)
781 {
782 u32 i;
783 int ret = 0;
784
785 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
786 ret = ov7251_write_reg(client, regs[i].addr,
787 OV7251_REG_VALUE_08BIT, regs[i].val);
788 }
789 return ret;
790 }
791
792 /* Read registers up to 4 at a time */
ov7251_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)793 static int ov7251_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
794 u32 *val)
795 {
796 struct i2c_msg msgs[2];
797 u8 *data_be_p;
798 __be32 data_be = 0;
799 __be16 reg_addr_be = cpu_to_be16(reg);
800 int ret;
801
802 if (len > 4 || !len)
803 return -EINVAL;
804
805 data_be_p = (u8 *)&data_be;
806 /* Write register address */
807 msgs[0].addr = client->addr;
808 msgs[0].flags = 0;
809 msgs[0].len = 2;
810 msgs[0].buf = (u8 *)®_addr_be;
811
812 /* Read data from register */
813 msgs[1].addr = client->addr;
814 msgs[1].flags = I2C_M_RD;
815 msgs[1].len = len;
816 msgs[1].buf = &data_be_p[4 - len];
817
818 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
819 if (ret != ARRAY_SIZE(msgs))
820 return -EIO;
821
822 *val = be32_to_cpu(data_be);
823
824 return 0;
825 }
826
827
828
ov7251_get_reso_dist(const struct ov7251_mode * mode,struct v4l2_mbus_framefmt * framefmt)829 static int ov7251_get_reso_dist(const struct ov7251_mode *mode,
830 struct v4l2_mbus_framefmt *framefmt)
831 {
832 return abs(mode->width - framefmt->width) +
833 abs(mode->height - framefmt->height);
834 }
835
836 static const struct ov7251_mode *
ov7251_find_best_fit(struct v4l2_subdev_format * fmt)837 ov7251_find_best_fit(struct v4l2_subdev_format *fmt)
838 {
839 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
840 int dist;
841 int cur_best_fit = 0;
842 int cur_best_fit_dist = -1;
843 unsigned int i;
844
845 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
846 dist = ov7251_get_reso_dist(&supported_modes[i], framefmt);
847 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
848 cur_best_fit_dist = dist;
849 cur_best_fit = i;
850 }
851 }
852
853 return &supported_modes[cur_best_fit];
854 }
855
ov7251_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)856 static int ov7251_set_fmt(struct v4l2_subdev *sd,
857 struct v4l2_subdev_pad_config *cfg,
858 struct v4l2_subdev_format *fmt)
859 {
860 struct ov7251 *ov7251 = to_ov7251(sd);
861 const struct ov7251_mode *mode;
862 s64 h_blank, vblank_def;
863
864 mutex_lock(&ov7251->mutex);
865
866 mode = ov7251_find_best_fit(fmt);
867 fmt->format.code = mode->bus_fmt;
868 fmt->format.width = mode->width;
869 fmt->format.height = mode->height;
870 fmt->format.field = V4L2_FIELD_NONE;
871 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
872 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
873 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
874 #else
875 mutex_unlock(&ov7251->mutex);
876 return -ENOTTY;
877 #endif
878 } else {
879 ov7251->cur_mode = mode;
880 h_blank = mode->hts_def - mode->width;
881 __v4l2_ctrl_modify_range(ov7251->hblank, h_blank,
882 h_blank, 1, h_blank);
883 vblank_def = mode->vts_def - mode->height;
884 __v4l2_ctrl_modify_range(ov7251->vblank, vblank_def,
885 OV7251_VTS_MAX - mode->height,
886 1, vblank_def);
887 ov7251->cur_fps = mode->max_fps;
888 }
889
890 mutex_unlock(&ov7251->mutex);
891
892 return 0;
893 }
894
ov7251_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)895 static int ov7251_get_fmt(struct v4l2_subdev *sd,
896 struct v4l2_subdev_pad_config *cfg,
897 struct v4l2_subdev_format *fmt)
898 {
899 struct ov7251 *ov7251 = to_ov7251(sd);
900 const struct ov7251_mode *mode = ov7251->cur_mode;
901
902 mutex_lock(&ov7251->mutex);
903 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
904 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
905 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
906 #else
907 mutex_unlock(&ov7251->mutex);
908 return -ENOTTY;
909 #endif
910 } else {
911 fmt->format.width = mode->width;
912 fmt->format.height = mode->height;
913 fmt->format.code = mode->bus_fmt;
914 fmt->format.field = V4L2_FIELD_NONE;
915 /* format info: width/height/data type/virctual channel */
916 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
917 fmt->reserved[0] = mode->vc[fmt->pad];
918 else
919 fmt->reserved[0] = mode->vc[PAD0];
920 }
921 mutex_unlock(&ov7251->mutex);
922
923 return 0;
924 }
925
ov7251_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)926 static int ov7251_enum_mbus_code(struct v4l2_subdev *sd,
927 struct v4l2_subdev_pad_config *cfg,
928 struct v4l2_subdev_mbus_code_enum *code)
929 {
930 struct ov7251 *ov7251 = to_ov7251(sd);
931
932 if (code->index != 0)
933 return -EINVAL;
934 code->code = ov7251->cur_mode->bus_fmt;
935
936 return 0;
937 }
938
ov7251_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)939 static int ov7251_enum_frame_sizes(struct v4l2_subdev *sd,
940 struct v4l2_subdev_pad_config *cfg,
941 struct v4l2_subdev_frame_size_enum *fse)
942 {
943 if (fse->index >= ARRAY_SIZE(supported_modes))
944 return -EINVAL;
945
946 if (fse->code != supported_modes[0].bus_fmt)
947 return -EINVAL;
948
949 fse->min_width = supported_modes[fse->index].width;
950 fse->max_width = supported_modes[fse->index].width;
951 fse->max_height = supported_modes[fse->index].height;
952 fse->min_height = supported_modes[fse->index].height;
953
954 return 0;
955 }
956
ov7251_enable_test_pattern(struct ov7251 * ov7251,u32 pattern)957 static int ov7251_enable_test_pattern(struct ov7251 *ov7251, u32 pattern)
958 {
959 u32 val;
960
961 if (pattern)
962 val = (pattern - 1) | OV7251_TEST_PATTERN_ENABLE;
963 else
964 val = OV7251_TEST_PATTERN_DISABLE;
965
966 return ov7251_write_reg(ov7251->client, OV7251_REG_TEST_PATTERN,
967 OV7251_REG_VALUE_08BIT, val);
968 }
969
ov7251_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)970 static int ov7251_g_frame_interval(struct v4l2_subdev *sd,
971 struct v4l2_subdev_frame_interval *fi)
972 {
973 struct ov7251 *ov7251 = to_ov7251(sd);
974 const struct ov7251_mode *mode = ov7251->cur_mode;
975
976 if (ov7251->streaming)
977 fi->interval = ov7251->cur_fps;
978 else
979 fi->interval = mode->max_fps;
980
981 return 0;
982 }
983
ov7251_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)984 static int ov7251_g_mbus_config(struct v4l2_subdev *sd,
985 unsigned int pad_id,
986 struct v4l2_mbus_config *config)
987 {
988 struct ov7251 *ov7251 = to_ov7251(sd);
989 const struct ov7251_mode *mode = ov7251->cur_mode;
990 u32 val = 1 << (OV7251_LANES - 1) |
991 V4L2_MBUS_CSI2_CHANNEL_0 |
992 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
993
994 if (mode->hdr_mode != NO_HDR)
995 val |= V4L2_MBUS_CSI2_CHANNEL_1;
996 if (mode->hdr_mode == HDR_X3)
997 val |= V4L2_MBUS_CSI2_CHANNEL_2;
998
999 config->type = V4L2_MBUS_CSI2_DPHY;
1000 config->flags = val;
1001
1002 return 0;
1003 }
1004
ov7251_get_module_inf(struct ov7251 * ov7251,struct rkmodule_inf * inf)1005 static void ov7251_get_module_inf(struct ov7251 *ov7251,
1006 struct rkmodule_inf *inf)
1007 {
1008 memset(inf, 0, sizeof(*inf));
1009 strscpy(inf->base.sensor, OV7251_NAME, sizeof(inf->base.sensor));
1010 strscpy(inf->base.module, ov7251->module_name,
1011 sizeof(inf->base.module));
1012 strscpy(inf->base.lens, ov7251->len_name, sizeof(inf->base.lens));
1013 }
1014
ov7251_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1015 static long ov7251_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1016 {
1017 struct ov7251 *ov7251 = to_ov7251(sd);
1018 struct rkmodule_hdr_cfg *hdr;
1019 u32 i, h, w;
1020 long ret = 0;
1021 u32 stream = 0;
1022
1023 switch (cmd) {
1024 case RKMODULE_GET_MODULE_INFO:
1025 ov7251_get_module_inf(ov7251, (struct rkmodule_inf *)arg);
1026 break;
1027 case RKMODULE_GET_HDR_CFG:
1028 hdr = (struct rkmodule_hdr_cfg *)arg;
1029 hdr->esp.mode = HDR_NORMAL_VC;
1030 hdr->hdr_mode = ov7251->cur_mode->hdr_mode;
1031 break;
1032 case RKMODULE_SET_HDR_CFG:
1033 hdr = (struct rkmodule_hdr_cfg *)arg;
1034 w = ov7251->cur_mode->width;
1035 h = ov7251->cur_mode->height;
1036 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1037 if (w == supported_modes[i].width &&
1038 h == supported_modes[i].height &&
1039 supported_modes[i].hdr_mode == hdr->hdr_mode) {
1040 ov7251->cur_mode = &supported_modes[i];
1041 break;
1042 }
1043 }
1044 if (i == ARRAY_SIZE(supported_modes)) {
1045 dev_err(&ov7251->client->dev,
1046 "not find hdr mode:%d %dx%d config\n",
1047 hdr->hdr_mode, w, h);
1048 ret = -EINVAL;
1049 } else {
1050 w = ov7251->cur_mode->hts_def - ov7251->cur_mode->width;
1051 h = ov7251->cur_mode->vts_def - ov7251->cur_mode->height;
1052 __v4l2_ctrl_modify_range(ov7251->hblank, w, w, 1, w);
1053 __v4l2_ctrl_modify_range(ov7251->vblank, h,
1054 OV7251_VTS_MAX - ov7251->cur_mode->height, 1, h);
1055 }
1056 break;
1057 case PREISP_CMD_SET_HDRAE_EXP:
1058 break;
1059 case RKMODULE_SET_QUICK_STREAM:
1060
1061 stream = *((u32 *)arg);
1062
1063 if (stream)
1064 ret = ov7251_write_reg(ov7251->client, OV7251_REG_CTRL_MODE,
1065 OV7251_REG_VALUE_08BIT, OV7251_MODE_STREAMING);
1066 else
1067 ret = ov7251_write_reg(ov7251->client, OV7251_REG_CTRL_MODE,
1068 OV7251_REG_VALUE_08BIT, OV7251_MODE_SW_STANDBY);
1069 break;
1070 default:
1071 ret = -ENOIOCTLCMD;
1072 break;
1073 }
1074
1075 return ret;
1076 }
1077
1078 #ifdef CONFIG_COMPAT
ov7251_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1079 static long ov7251_compat_ioctl32(struct v4l2_subdev *sd,
1080 unsigned int cmd, unsigned long arg)
1081 {
1082 void __user *up = compat_ptr(arg);
1083 struct rkmodule_inf *inf;
1084 struct rkmodule_hdr_cfg *hdr;
1085 struct preisp_hdrae_exp_s *hdrae;
1086 long ret;
1087 u32 stream = 0;
1088
1089 switch (cmd) {
1090 case RKMODULE_GET_MODULE_INFO:
1091 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1092 if (!inf) {
1093 ret = -ENOMEM;
1094 return ret;
1095 }
1096
1097 ret = ov7251_ioctl(sd, cmd, inf);
1098 if (!ret) {
1099 if (copy_to_user(up, inf, sizeof(*inf)))
1100 ret = -EFAULT;
1101 }
1102 kfree(inf);
1103 break;
1104 case RKMODULE_GET_HDR_CFG:
1105 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1106 if (!hdr) {
1107 ret = -ENOMEM;
1108 return ret;
1109 }
1110
1111 ret = ov7251_ioctl(sd, cmd, hdr);
1112 if (!ret) {
1113 if (copy_to_user(up, hdr, sizeof(*hdr)))
1114 ret = -EFAULT;
1115 }
1116 kfree(hdr);
1117 break;
1118 case RKMODULE_SET_HDR_CFG:
1119 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1120 if (!hdr) {
1121 ret = -ENOMEM;
1122 return ret;
1123 }
1124
1125 ret = copy_from_user(hdr, up, sizeof(*hdr));
1126 if (!ret)
1127 ret = ov7251_ioctl(sd, cmd, hdr);
1128 else
1129 ret = -EFAULT;
1130 kfree(hdr);
1131 break;
1132 case PREISP_CMD_SET_HDRAE_EXP:
1133 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1134 if (!hdrae) {
1135 ret = -ENOMEM;
1136 return ret;
1137 }
1138
1139 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
1140 if (!ret)
1141 ret = ov7251_ioctl(sd, cmd, hdrae);
1142 else
1143 ret = -EFAULT;
1144 kfree(hdrae);
1145 break;
1146 case RKMODULE_SET_QUICK_STREAM:
1147 ret = copy_from_user(&stream, up, sizeof(u32));
1148 if (!ret)
1149 ret = ov7251_ioctl(sd, cmd, &stream);
1150 else
1151 ret = -EFAULT;
1152 break;
1153 default:
1154 ret = -ENOIOCTLCMD;
1155 break;
1156 }
1157
1158 return ret;
1159 }
1160 #endif
1161
__ov7251_start_stream(struct ov7251 * ov7251)1162 static int __ov7251_start_stream(struct ov7251 *ov7251)
1163 {
1164 int ret;
1165
1166 ret = ov7251_write_array(ov7251->client, ov7251->cur_mode->reg_list);
1167 if (ret)
1168 return ret;
1169
1170 /* In case these controls are set before streaming */
1171 ret = __v4l2_ctrl_handler_setup(&ov7251->ctrl_handler);
1172 if (ret)
1173 return ret;
1174
1175 return ov7251_write_reg(ov7251->client, OV7251_REG_CTRL_MODE,
1176 OV7251_REG_VALUE_08BIT, OV7251_MODE_STREAMING);
1177 }
1178
__ov7251_stop_stream(struct ov7251 * ov7251)1179 static int __ov7251_stop_stream(struct ov7251 *ov7251)
1180 {
1181 return ov7251_write_reg(ov7251->client, OV7251_REG_CTRL_MODE,
1182 OV7251_REG_VALUE_08BIT, OV7251_MODE_SW_STANDBY);
1183 }
1184
ov7251_s_stream(struct v4l2_subdev * sd,int on)1185 static int ov7251_s_stream(struct v4l2_subdev *sd, int on)
1186 {
1187 struct ov7251 *ov7251 = to_ov7251(sd);
1188 struct i2c_client *client = ov7251->client;
1189 int ret = 0;
1190
1191 mutex_lock(&ov7251->mutex);
1192 on = !!on;
1193 if (on == ov7251->streaming)
1194 goto unlock_and_return;
1195
1196 if (on) {
1197 ret = pm_runtime_get_sync(&client->dev);
1198 if (ret < 0) {
1199 pm_runtime_put_noidle(&client->dev);
1200 goto unlock_and_return;
1201 }
1202
1203 ret = __ov7251_start_stream(ov7251);
1204 if (ret) {
1205 v4l2_err(sd, "start stream failed while write regs\n");
1206 pm_runtime_put(&client->dev);
1207 goto unlock_and_return;
1208 }
1209 usleep_range(10 * 1000, 12 * 1000);
1210 } else {
1211 __ov7251_stop_stream(ov7251);
1212 pm_runtime_put(&client->dev);
1213 }
1214
1215 ov7251->streaming = on;
1216
1217 unlock_and_return:
1218 mutex_unlock(&ov7251->mutex);
1219
1220 return ret;
1221 }
1222
ov7251_s_power(struct v4l2_subdev * sd,int on)1223 static int ov7251_s_power(struct v4l2_subdev *sd, int on)
1224 {
1225 struct ov7251 *ov7251 = to_ov7251(sd);
1226 struct i2c_client *client = ov7251->client;
1227 int ret = 0;
1228
1229 mutex_lock(&ov7251->mutex);
1230
1231 /* If the power state is not modified - no work to do. */
1232 if (ov7251->power_on == !!on)
1233 goto unlock_and_return;
1234
1235 if (on) {
1236 ret = pm_runtime_get_sync(&client->dev);
1237 if (ret < 0) {
1238 pm_runtime_put_noidle(&client->dev);
1239 goto unlock_and_return;
1240 }
1241
1242 ret = ov7251_write_array(ov7251->client, ov7251_global_regs);
1243 if (ret) {
1244 v4l2_err(sd, "could not set init registers\n");
1245 pm_runtime_put_noidle(&client->dev);
1246 goto unlock_and_return;
1247 }
1248
1249 ov7251->power_on = true;
1250 } else {
1251 pm_runtime_put(&client->dev);
1252 ov7251->power_on = false;
1253 }
1254
1255 unlock_and_return:
1256 mutex_unlock(&ov7251->mutex);
1257
1258 return ret;
1259 }
1260
1261 /* Calculate the delay in us by clock rate and clock cycles */
ov7251_cal_delay(u32 cycles)1262 static inline u32 ov7251_cal_delay(u32 cycles)
1263 {
1264 return DIV_ROUND_UP(cycles, OV7251_XVCLK_FREQ / 1000 / 1000);
1265 }
1266
__ov7251_power_on(struct ov7251 * ov7251)1267 static int __ov7251_power_on(struct ov7251 *ov7251)
1268 {
1269 int ret;
1270 u32 delay_us;
1271 struct device *dev = &ov7251->client->dev;
1272
1273 if (!IS_ERR_OR_NULL(ov7251->pins_default)) {
1274 ret = pinctrl_select_state(ov7251->pinctrl,
1275 ov7251->pins_default);
1276 if (ret < 0)
1277 dev_err(dev, "could not set pins\n");
1278 }
1279 ret = clk_set_rate(ov7251->xvclk, OV7251_XVCLK_FREQ);
1280 if (ret < 0)
1281 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1282 if (clk_get_rate(ov7251->xvclk) != OV7251_XVCLK_FREQ)
1283 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1284 ret = clk_prepare_enable(ov7251->xvclk);
1285 if (ret < 0) {
1286 dev_err(dev, "Failed to enable xvclk\n");
1287 return ret;
1288 }
1289
1290 if (!IS_ERR(ov7251->reset_gpio))
1291 gpiod_set_value_cansleep(ov7251->reset_gpio, 0);
1292
1293 ret = regulator_bulk_enable(OV7251_NUM_SUPPLIES, ov7251->supplies);
1294 if (ret < 0) {
1295 dev_err(dev, "Failed to enable regulators\n");
1296 goto disable_clk;
1297 }
1298
1299 usleep_range(5 * 1000, 10 * 1000);
1300 if (!IS_ERR(ov7251->reset_gpio))
1301 gpiod_set_value_cansleep(ov7251->reset_gpio, 1);
1302
1303 usleep_range(500, 1000);
1304 if (!IS_ERR(ov7251->pwdn_gpio))
1305 gpiod_set_value_cansleep(ov7251->pwdn_gpio, 1);
1306
1307 if (!IS_ERR(ov7251->reset_gpio))
1308 usleep_range(6000, 8000);
1309 else
1310 usleep_range(12000, 16000);
1311
1312 /* 8192 cycles prior to first SCCB transaction */
1313 delay_us = ov7251_cal_delay(8192);
1314 usleep_range(delay_us, delay_us * 2);
1315
1316 return 0;
1317
1318 disable_clk:
1319 clk_disable_unprepare(ov7251->xvclk);
1320
1321 return ret;
1322 }
1323
__ov7251_power_off(struct ov7251 * ov7251)1324 static void __ov7251_power_off(struct ov7251 *ov7251)
1325 {
1326 int ret;
1327 struct device *dev = &ov7251->client->dev;
1328
1329 if (!IS_ERR(ov7251->pwdn_gpio))
1330 gpiod_set_value_cansleep(ov7251->pwdn_gpio, 0);
1331 clk_disable_unprepare(ov7251->xvclk);
1332 if (!IS_ERR(ov7251->reset_gpio))
1333 gpiod_set_value_cansleep(ov7251->reset_gpio, 0);
1334 if (!IS_ERR_OR_NULL(ov7251->pins_sleep)) {
1335 ret = pinctrl_select_state(ov7251->pinctrl,
1336 ov7251->pins_sleep);
1337 if (ret < 0)
1338 dev_dbg(dev, "could not set pins\n");
1339 }
1340 regulator_bulk_disable(OV7251_NUM_SUPPLIES, ov7251->supplies);
1341 }
1342
ov7251_runtime_resume(struct device * dev)1343 static int ov7251_runtime_resume(struct device *dev)
1344 {
1345 struct i2c_client *client = to_i2c_client(dev);
1346 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1347 struct ov7251 *ov7251 = to_ov7251(sd);
1348
1349 return __ov7251_power_on(ov7251);
1350 }
1351
ov7251_runtime_suspend(struct device * dev)1352 static int ov7251_runtime_suspend(struct device *dev)
1353 {
1354 struct i2c_client *client = to_i2c_client(dev);
1355 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1356 struct ov7251 *ov7251 = to_ov7251(sd);
1357
1358 __ov7251_power_off(ov7251);
1359
1360 return 0;
1361 }
1362
1363 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov7251_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1364 static int ov7251_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1365 {
1366 struct ov7251 *ov7251 = to_ov7251(sd);
1367 struct v4l2_mbus_framefmt *try_fmt =
1368 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1369 const struct ov7251_mode *def_mode = &supported_modes[0];
1370
1371 mutex_lock(&ov7251->mutex);
1372 /* Initialize try_fmt */
1373 try_fmt->width = def_mode->width;
1374 try_fmt->height = def_mode->height;
1375 try_fmt->code = def_mode->bus_fmt;
1376 try_fmt->field = V4L2_FIELD_NONE;
1377
1378 mutex_unlock(&ov7251->mutex);
1379 /* No crop or compose */
1380
1381 return 0;
1382 }
1383 #endif
1384
ov7251_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1385 static int ov7251_enum_frame_interval(struct v4l2_subdev *sd,
1386 struct v4l2_subdev_pad_config *cfg,
1387 struct v4l2_subdev_frame_interval_enum *fie)
1388 {
1389 if (fie->index >= ARRAY_SIZE(supported_modes))
1390 return -EINVAL;
1391
1392 fie->code = supported_modes[fie->index].bus_fmt;
1393 fie->width = supported_modes[fie->index].width;
1394 fie->height = supported_modes[fie->index].height;
1395 fie->interval = supported_modes[fie->index].max_fps;
1396 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1397 return 0;
1398 }
1399
1400 static const struct dev_pm_ops ov7251_pm_ops = {
1401 SET_RUNTIME_PM_OPS(ov7251_runtime_suspend,
1402 ov7251_runtime_resume, NULL)
1403 };
1404
1405 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1406 static const struct v4l2_subdev_internal_ops ov7251_internal_ops = {
1407 .open = ov7251_open,
1408 };
1409 #endif
1410
1411 static const struct v4l2_subdev_core_ops ov7251_core_ops = {
1412 .s_power = ov7251_s_power,
1413 .ioctl = ov7251_ioctl,
1414 #ifdef CONFIG_COMPAT
1415 .compat_ioctl32 = ov7251_compat_ioctl32,
1416 #endif
1417 };
1418
1419 static const struct v4l2_subdev_video_ops ov7251_video_ops = {
1420 .s_stream = ov7251_s_stream,
1421 .g_frame_interval = ov7251_g_frame_interval,
1422 };
1423
1424 static const struct v4l2_subdev_pad_ops ov7251_pad_ops = {
1425 .enum_mbus_code = ov7251_enum_mbus_code,
1426 .enum_frame_size = ov7251_enum_frame_sizes,
1427 .enum_frame_interval = ov7251_enum_frame_interval,
1428 .get_fmt = ov7251_get_fmt,
1429 .set_fmt = ov7251_set_fmt,
1430 .get_mbus_config = ov7251_g_mbus_config,
1431 };
1432
1433 static const struct v4l2_subdev_ops ov7251_subdev_ops = {
1434 .core = &ov7251_core_ops,
1435 .video = &ov7251_video_ops,
1436 .pad = &ov7251_pad_ops,
1437 };
1438
ov7251_set_ctrl(struct v4l2_ctrl * ctrl)1439 static int ov7251_set_ctrl(struct v4l2_ctrl *ctrl)
1440 {
1441 struct ov7251 *ov7251 = container_of(ctrl->handler,
1442 struct ov7251, ctrl_handler);
1443 struct i2c_client *client = ov7251->client;
1444 s64 max;
1445 int ret = 0;
1446 u32 val = 0;
1447
1448 /* Propagate change of current control to all related controls */
1449 switch (ctrl->id) {
1450 case V4L2_CID_VBLANK:
1451 /* Update max exposure while meeting expected vblanking */
1452 max = ov7251->cur_mode->height + ctrl->val - 20;
1453 __v4l2_ctrl_modify_range(ov7251->exposure,
1454 ov7251->exposure->minimum, max,
1455 ov7251->exposure->step,
1456 ov7251->exposure->default_value);
1457 break;
1458 }
1459
1460 if (!pm_runtime_get_if_in_use(&client->dev))
1461 return 0;
1462
1463 switch (ctrl->id) {
1464 case V4L2_CID_EXPOSURE:
1465 /* 4 least significant bits of expsoure are fractional part */
1466 ret = ov7251_write_reg(ov7251->client, OV7251_REG_EXPOSURE,
1467 OV7251_REG_VALUE_24BIT, ctrl->val << 4);
1468 break;
1469 case V4L2_CID_ANALOGUE_GAIN:
1470 ret = ov7251_write_reg(ov7251->client, OV7251_REG_ANALOG_GAIN,
1471 OV7251_REG_VALUE_16BIT,
1472 ctrl->val & ANALOG_GAIN_MASK);
1473 break;
1474 case V4L2_CID_VBLANK:
1475 ret = ov7251_write_reg(ov7251->client, OV7251_REG_VTS,
1476 OV7251_REG_VALUE_16BIT,
1477 ctrl->val + ov7251->cur_mode->height);
1478 break;
1479 case V4L2_CID_TEST_PATTERN:
1480 ret = ov7251_enable_test_pattern(ov7251, ctrl->val);
1481 break;
1482 case V4L2_CID_HFLIP:
1483 ret = ov7251_read_reg(ov7251->client, OV7251_MIRROR_REG,
1484 OV7251_REG_VALUE_08BIT, &val);
1485 ret |= ov7251_write_reg(ov7251->client, OV7251_MIRROR_REG,
1486 OV7251_REG_VALUE_08BIT,
1487 OV7251_FETCH_MIRROR(val, ctrl->val));
1488 break;
1489 case V4L2_CID_VFLIP:
1490 ret = ov7251_read_reg(ov7251->client, OV7251_FLIP_REG,
1491 OV7251_REG_VALUE_08BIT, &val);
1492 ret |= ov7251_write_reg(ov7251->client, OV7251_FLIP_REG,
1493 OV7251_REG_VALUE_08BIT,
1494 OV7251_FETCH_FLIP(val, ctrl->val));
1495 break;
1496
1497 default:
1498 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1499 __func__, ctrl->id, ctrl->val);
1500 break;
1501 }
1502
1503 pm_runtime_put(&client->dev);
1504
1505 return ret;
1506 }
1507
1508 static const struct v4l2_ctrl_ops ov7251_ctrl_ops = {
1509 .s_ctrl = ov7251_set_ctrl,
1510 };
1511
ov7251_initialize_controls(struct ov7251 * ov7251)1512 static int ov7251_initialize_controls(struct ov7251 *ov7251)
1513 {
1514 const struct ov7251_mode *mode;
1515 struct v4l2_ctrl_handler *handler;
1516 struct v4l2_ctrl *ctrl;
1517 s64 exposure_max, vblank_def;
1518 u32 h_blank;
1519 int ret;
1520
1521 handler = &ov7251->ctrl_handler;
1522 mode = ov7251->cur_mode;
1523 ret = v4l2_ctrl_handler_init(handler, 9);
1524 if (ret)
1525 return ret;
1526 handler->lock = &ov7251->mutex;
1527
1528 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1529 0, 0, link_freq_menu_items);
1530 if (ctrl)
1531 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1532
1533 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1534 0, PIXEL_RATE_WITH_240M_10BIT, 1, PIXEL_RATE_WITH_240M_10BIT);
1535
1536 h_blank = mode->hts_def - mode->width;
1537 ov7251->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1538 h_blank, h_blank, 1, h_blank);
1539 if (ov7251->hblank)
1540 ov7251->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1541 vblank_def = mode->vts_def - mode->height;
1542 ov7251->vblank = v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
1543 V4L2_CID_VBLANK, vblank_def,
1544 OV7251_VTS_MAX - mode->height,
1545 1, vblank_def);
1546 ov7251->cur_fps = mode->max_fps;
1547 exposure_max = mode->vts_def - 20;
1548 ov7251->exposure = v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
1549 V4L2_CID_EXPOSURE, OV7251_EXPOSURE_MIN,
1550 exposure_max, OV7251_EXPOSURE_STEP,
1551 mode->exp_def);
1552 ov7251->anal_gain = v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
1553 V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1554 ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1555 ANALOG_GAIN_DEFAULT);
1556
1557 ov7251->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1558 &ov7251_ctrl_ops,
1559 V4L2_CID_TEST_PATTERN,
1560 ARRAY_SIZE(ov7251_test_pattern_menu) - 1,
1561 0, 0, ov7251_test_pattern_menu);
1562 v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
1563 V4L2_CID_HFLIP, 0, 1, 1, 0);
1564 v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
1565 V4L2_CID_VFLIP, 0, 1, 1, 0);
1566 if (handler->error) {
1567 ret = handler->error;
1568 dev_err(&ov7251->client->dev,
1569 "Failed to init controls(%d)\n", ret);
1570 goto err_free_handler;
1571 }
1572
1573 ov7251->subdev.ctrl_handler = handler;
1574
1575 return 0;
1576
1577 err_free_handler:
1578 v4l2_ctrl_handler_free(handler);
1579
1580 return ret;
1581 }
1582
ov7251_check_sensor_id(struct ov7251 * ov7251,struct i2c_client * client)1583 static int ov7251_check_sensor_id(struct ov7251 *ov7251,
1584 struct i2c_client *client)
1585 {
1586 struct device *dev = &ov7251->client->dev;
1587 u32 id = 0;
1588 int ret;
1589
1590 ret = ov7251_read_reg(client, OV7251_REG_CHIP_ID,
1591 OV7251_REG_VALUE_08BIT, &id);
1592 if (id != CHIP_ID) {
1593 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1594 return -ENODEV;
1595 }
1596
1597 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1598
1599 return 0;
1600 }
1601
ov7251_configure_regulators(struct ov7251 * ov7251)1602 static int ov7251_configure_regulators(struct ov7251 *ov7251)
1603 {
1604 unsigned int i;
1605
1606 for (i = 0; i < OV7251_NUM_SUPPLIES; i++)
1607 ov7251->supplies[i].supply = ov7251_supply_names[i];
1608
1609 return devm_regulator_bulk_get(&ov7251->client->dev,
1610 OV7251_NUM_SUPPLIES,
1611 ov7251->supplies);
1612 }
1613
ov7251_probe(struct i2c_client * client,const struct i2c_device_id * id)1614 static int ov7251_probe(struct i2c_client *client,
1615 const struct i2c_device_id *id)
1616 {
1617 struct device *dev = &client->dev;
1618 struct device_node *node = dev->of_node;
1619 struct ov7251 *ov7251;
1620 struct v4l2_subdev *sd;
1621 char facing[2];
1622 int ret;
1623
1624 dev_info(dev, "driver version: %02x.%02x.%02x",
1625 DRIVER_VERSION >> 16,
1626 (DRIVER_VERSION & 0xff00) >> 8,
1627 DRIVER_VERSION & 0x00ff);
1628
1629 ov7251 = devm_kzalloc(dev, sizeof(*ov7251), GFP_KERNEL);
1630 if (!ov7251)
1631 return -ENOMEM;
1632
1633 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1634 &ov7251->module_index);
1635 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1636 &ov7251->module_facing);
1637 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1638 &ov7251->module_name);
1639 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1640 &ov7251->len_name);
1641 if (ret) {
1642 dev_err(dev, "could not get module information!\n");
1643 return -EINVAL;
1644 }
1645
1646 ov7251->client = client;
1647 ov7251->cur_mode = &supported_modes[0];
1648
1649 ov7251->xvclk = devm_clk_get(dev, "xvclk");
1650 if (IS_ERR(ov7251->xvclk)) {
1651 dev_err(dev, "Failed to get xvclk\n");
1652 return -EINVAL;
1653 }
1654
1655 ov7251->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1656 if (IS_ERR(ov7251->reset_gpio))
1657 dev_warn(dev, "Failed to get reset-gpios\n");
1658
1659 ov7251->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1660 if (IS_ERR(ov7251->pwdn_gpio))
1661 dev_warn(dev, "Failed to get pwdn-gpios\n");
1662
1663 ov7251->pinctrl = devm_pinctrl_get(dev);
1664 if (!IS_ERR(ov7251->pinctrl)) {
1665 ov7251->pins_default =
1666 pinctrl_lookup_state(ov7251->pinctrl,
1667 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1668 if (IS_ERR(ov7251->pins_default))
1669 dev_err(dev, "could not get default pinstate\n");
1670
1671 ov7251->pins_sleep =
1672 pinctrl_lookup_state(ov7251->pinctrl,
1673 OF_CAMERA_PINCTRL_STATE_SLEEP);
1674 if (IS_ERR(ov7251->pins_sleep))
1675 dev_err(dev, "could not get sleep pinstate\n");
1676 } else {
1677 dev_err(dev, "no pinctrl\n");
1678 }
1679
1680 ret = ov7251_configure_regulators(ov7251);
1681 if (ret) {
1682 dev_err(dev, "Failed to get power regulators\n");
1683 return ret;
1684 }
1685
1686 mutex_init(&ov7251->mutex);
1687
1688 sd = &ov7251->subdev;
1689 v4l2_i2c_subdev_init(sd, client, &ov7251_subdev_ops);
1690 ret = ov7251_initialize_controls(ov7251);
1691 if (ret)
1692 goto err_destroy_mutex;
1693
1694 ret = __ov7251_power_on(ov7251);
1695 if (ret)
1696 goto err_free_handler;
1697
1698 ret = ov7251_check_sensor_id(ov7251, client);
1699 if (ret)
1700 goto err_power_off;
1701
1702 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1703 sd->internal_ops = &ov7251_internal_ops;
1704 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1705 V4L2_SUBDEV_FL_HAS_EVENTS;
1706 #endif
1707 #if defined(CONFIG_MEDIA_CONTROLLER)
1708 ov7251->pad.flags = MEDIA_PAD_FL_SOURCE;
1709 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1710 ret = media_entity_pads_init(&sd->entity, 1, &ov7251->pad);
1711 if (ret < 0)
1712 goto err_power_off;
1713 #endif
1714
1715 memset(facing, 0, sizeof(facing));
1716 if (strcmp(ov7251->module_facing, "back") == 0)
1717 facing[0] = 'b';
1718 else
1719 facing[0] = 'f';
1720
1721 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1722 ov7251->module_index, facing,
1723 OV7251_NAME, dev_name(sd->dev));
1724 ret = v4l2_async_register_subdev_sensor_common(sd);
1725 if (ret) {
1726 dev_err(dev, "v4l2 async register subdev failed\n");
1727 goto err_clean_entity;
1728 }
1729
1730 pm_runtime_set_active(dev);
1731 pm_runtime_enable(dev);
1732 pm_runtime_idle(dev);
1733
1734 return 0;
1735
1736 err_clean_entity:
1737 #if defined(CONFIG_MEDIA_CONTROLLER)
1738 media_entity_cleanup(&sd->entity);
1739 #endif
1740 err_power_off:
1741 __ov7251_power_off(ov7251);
1742 err_free_handler:
1743 v4l2_ctrl_handler_free(&ov7251->ctrl_handler);
1744 err_destroy_mutex:
1745 mutex_destroy(&ov7251->mutex);
1746
1747 return ret;
1748 }
1749
ov7251_remove(struct i2c_client * client)1750 static int ov7251_remove(struct i2c_client *client)
1751 {
1752 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1753 struct ov7251 *ov7251 = to_ov7251(sd);
1754
1755 v4l2_async_unregister_subdev(sd);
1756 #if defined(CONFIG_MEDIA_CONTROLLER)
1757 media_entity_cleanup(&sd->entity);
1758 #endif
1759 v4l2_ctrl_handler_free(&ov7251->ctrl_handler);
1760 mutex_destroy(&ov7251->mutex);
1761
1762 pm_runtime_disable(&client->dev);
1763 if (!pm_runtime_status_suspended(&client->dev))
1764 __ov7251_power_off(ov7251);
1765 pm_runtime_set_suspended(&client->dev);
1766
1767 return 0;
1768 }
1769
1770 #if IS_ENABLED(CONFIG_OF)
1771 static const struct of_device_id ov7251_of_match[] = {
1772 { .compatible = "ovti,ov7251" },
1773 {},
1774 };
1775 MODULE_DEVICE_TABLE(of, ov7251_of_match);
1776 #endif
1777
1778 static const struct i2c_device_id ov7251_match_id[] = {
1779 { "ovti,ov7251", 0 },
1780 { },
1781 };
1782
1783 static struct i2c_driver ov7251_i2c_driver = {
1784 .driver = {
1785 .name = OV7251_NAME,
1786 .pm = &ov7251_pm_ops,
1787 .of_match_table = of_match_ptr(ov7251_of_match),
1788 },
1789 .probe = &ov7251_probe,
1790 .remove = &ov7251_remove,
1791 .id_table = ov7251_match_id,
1792 };
1793
sensor_mod_init(void)1794 static int __init sensor_mod_init(void)
1795 {
1796 return i2c_add_driver(&ov7251_i2c_driver);
1797 }
1798
sensor_mod_exit(void)1799 static void __exit sensor_mod_exit(void)
1800 {
1801 i2c_del_driver(&ov7251_i2c_driver);
1802 }
1803
1804 device_initcall_sync(sensor_mod_init);
1805 module_exit(sensor_mod_exit);
1806
1807 MODULE_DESCRIPTION("OmniVision ov7251 sensor driver");
1808 MODULE_LICENSE("GPL v2");
1809