1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * AD9523 SPI Low Jitter Clock Generator 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2012 Analog Devices Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef IIO_FREQUENCY_AD9523_H_ 9*4882a593Smuzhiyun #define IIO_FREQUENCY_AD9523_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun enum outp_drv_mode { 12*4882a593Smuzhiyun TRISTATE, 13*4882a593Smuzhiyun LVPECL_8mA, 14*4882a593Smuzhiyun LVDS_4mA, 15*4882a593Smuzhiyun LVDS_7mA, 16*4882a593Smuzhiyun HSTL0_16mA, 17*4882a593Smuzhiyun HSTL1_8mA, 18*4882a593Smuzhiyun CMOS_CONF1, 19*4882a593Smuzhiyun CMOS_CONF2, 20*4882a593Smuzhiyun CMOS_CONF3, 21*4882a593Smuzhiyun CMOS_CONF4, 22*4882a593Smuzhiyun CMOS_CONF5, 23*4882a593Smuzhiyun CMOS_CONF6, 24*4882a593Smuzhiyun CMOS_CONF7, 25*4882a593Smuzhiyun CMOS_CONF8, 26*4882a593Smuzhiyun CMOS_CONF9 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun enum ref_sel_mode { 30*4882a593Smuzhiyun NONEREVERTIVE_STAY_ON_REFB, 31*4882a593Smuzhiyun REVERT_TO_REFA, 32*4882a593Smuzhiyun SELECT_REFA, 33*4882a593Smuzhiyun SELECT_REFB, 34*4882a593Smuzhiyun EXT_REF_SEL 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /** 38*4882a593Smuzhiyun * struct ad9523_channel_spec - Output channel configuration 39*4882a593Smuzhiyun * 40*4882a593Smuzhiyun * @channel_num: Output channel number. 41*4882a593Smuzhiyun * @divider_output_invert_en: Invert the polarity of the output clock. 42*4882a593Smuzhiyun * @sync_ignore_en: Ignore chip-level SYNC signal. 43*4882a593Smuzhiyun * @low_power_mode_en: Reduce power used in the differential output modes. 44*4882a593Smuzhiyun * @use_alt_clock_src: Channel divider uses alternative clk source. 45*4882a593Smuzhiyun * @output_dis: Disables, powers down the entire channel. 46*4882a593Smuzhiyun * @driver_mode: Output driver mode (logic level family). 47*4882a593Smuzhiyun * @divider_phase: Divider initial phase after a SYNC. Range 0..63 48*4882a593Smuzhiyun LSB = 1/2 of a period of the divider input clock. 49*4882a593Smuzhiyun * @channel_divider: 10-bit channel divider. 50*4882a593Smuzhiyun * @extended_name: Optional descriptive channel name. 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct ad9523_channel_spec { 54*4882a593Smuzhiyun unsigned channel_num; 55*4882a593Smuzhiyun bool divider_output_invert_en; 56*4882a593Smuzhiyun bool sync_ignore_en; 57*4882a593Smuzhiyun bool low_power_mode_en; 58*4882a593Smuzhiyun /* CH0..CH3 VCXO, CH4..CH9 VCO2 */ 59*4882a593Smuzhiyun bool use_alt_clock_src; 60*4882a593Smuzhiyun bool output_dis; 61*4882a593Smuzhiyun enum outp_drv_mode driver_mode; 62*4882a593Smuzhiyun unsigned char divider_phase; 63*4882a593Smuzhiyun unsigned short channel_divider; 64*4882a593Smuzhiyun char extended_name[16]; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun enum pll1_rzero_resistor { 68*4882a593Smuzhiyun RZERO_883_OHM, 69*4882a593Smuzhiyun RZERO_677_OHM, 70*4882a593Smuzhiyun RZERO_341_OHM, 71*4882a593Smuzhiyun RZERO_135_OHM, 72*4882a593Smuzhiyun RZERO_10_OHM, 73*4882a593Smuzhiyun RZERO_USE_EXT_RES = 8, 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun enum rpole2_resistor { 77*4882a593Smuzhiyun RPOLE2_900_OHM, 78*4882a593Smuzhiyun RPOLE2_450_OHM, 79*4882a593Smuzhiyun RPOLE2_300_OHM, 80*4882a593Smuzhiyun RPOLE2_225_OHM, 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun enum rzero_resistor { 84*4882a593Smuzhiyun RZERO_3250_OHM, 85*4882a593Smuzhiyun RZERO_2750_OHM, 86*4882a593Smuzhiyun RZERO_2250_OHM, 87*4882a593Smuzhiyun RZERO_2100_OHM, 88*4882a593Smuzhiyun RZERO_3000_OHM, 89*4882a593Smuzhiyun RZERO_2500_OHM, 90*4882a593Smuzhiyun RZERO_2000_OHM, 91*4882a593Smuzhiyun RZERO_1850_OHM, 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun enum cpole1_capacitor { 95*4882a593Smuzhiyun CPOLE1_0_PF, 96*4882a593Smuzhiyun CPOLE1_8_PF, 97*4882a593Smuzhiyun CPOLE1_16_PF, 98*4882a593Smuzhiyun CPOLE1_24_PF, 99*4882a593Smuzhiyun _CPOLE1_24_PF, /* place holder */ 100*4882a593Smuzhiyun CPOLE1_32_PF, 101*4882a593Smuzhiyun CPOLE1_40_PF, 102*4882a593Smuzhiyun CPOLE1_48_PF, 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /** 106*4882a593Smuzhiyun * struct ad9523_platform_data - platform specific information 107*4882a593Smuzhiyun * 108*4882a593Smuzhiyun * @vcxo_freq: External VCXO frequency in Hz 109*4882a593Smuzhiyun * @refa_diff_rcv_en: REFA differential/single-ended input selection. 110*4882a593Smuzhiyun * @refb_diff_rcv_en: REFB differential/single-ended input selection. 111*4882a593Smuzhiyun * @zd_in_diff_en: Zero Delay differential/single-ended input selection. 112*4882a593Smuzhiyun * @osc_in_diff_en: OSC differential/ single-ended input selection. 113*4882a593Smuzhiyun * @refa_cmos_neg_inp_en: REFA single-ended neg./pos. input enable. 114*4882a593Smuzhiyun * @refb_cmos_neg_inp_en: REFB single-ended neg./pos. input enable. 115*4882a593Smuzhiyun * @zd_in_cmos_neg_inp_en: Zero Delay single-ended neg./pos. input enable. 116*4882a593Smuzhiyun * @osc_in_cmos_neg_inp_en: OSC single-ended neg./pos. input enable. 117*4882a593Smuzhiyun * @refa_r_div: PLL1 10-bit REFA R divider. 118*4882a593Smuzhiyun * @refb_r_div: PLL1 10-bit REFB R divider. 119*4882a593Smuzhiyun * @pll1_feedback_div: PLL1 10-bit Feedback N divider. 120*4882a593Smuzhiyun * @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA). 121*4882a593Smuzhiyun * @zero_delay_mode_internal_en: Internal, external Zero Delay mode selection. 122*4882a593Smuzhiyun * @osc_in_feedback_en: PLL1 feedback path, local feedback from 123*4882a593Smuzhiyun * the OSC_IN receiver or zero delay mode 124*4882a593Smuzhiyun * @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection. 125*4882a593Smuzhiyun * @ref_mode: Reference selection mode. 126*4882a593Smuzhiyun * @pll2_charge_pump_current_nA: Magnitude of PLL2 charge pump current (nA). 127*4882a593Smuzhiyun * @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4. 128*4882a593Smuzhiyun * @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63. 129*4882a593Smuzhiyun * @pll2_freq_doubler_en: PLL2 frequency doubler enable. 130*4882a593Smuzhiyun * @pll2_r2_div: PLL2 R2 divider, range 0..31. 131*4882a593Smuzhiyun * @pll2_vco_div_m1: VCO1 divider, range 3..5. 132*4882a593Smuzhiyun * @pll2_vco_div_m2: VCO2 divider, range 3..5. 133*4882a593Smuzhiyun * @rpole2: PLL2 loop filter Rpole resistor value. 134*4882a593Smuzhiyun * @rzero: PLL2 loop filter Rzero resistor value. 135*4882a593Smuzhiyun * @cpole1: PLL2 loop filter Cpole capacitor value. 136*4882a593Smuzhiyun * @rzero_bypass_en: PLL2 loop filter Rzero bypass enable. 137*4882a593Smuzhiyun * @num_channels: Array size of struct ad9523_channel_spec. 138*4882a593Smuzhiyun * @channels: Pointer to channel array. 139*4882a593Smuzhiyun * @name: Optional alternative iio device name. 140*4882a593Smuzhiyun */ 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun struct ad9523_platform_data { 143*4882a593Smuzhiyun unsigned long vcxo_freq; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* Differential/ Single-Ended Input Configuration */ 146*4882a593Smuzhiyun bool refa_diff_rcv_en; 147*4882a593Smuzhiyun bool refb_diff_rcv_en; 148*4882a593Smuzhiyun bool zd_in_diff_en; 149*4882a593Smuzhiyun bool osc_in_diff_en; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* 152*4882a593Smuzhiyun * Valid if differential input disabled 153*4882a593Smuzhiyun * if false defaults to pos input 154*4882a593Smuzhiyun */ 155*4882a593Smuzhiyun bool refa_cmos_neg_inp_en; 156*4882a593Smuzhiyun bool refb_cmos_neg_inp_en; 157*4882a593Smuzhiyun bool zd_in_cmos_neg_inp_en; 158*4882a593Smuzhiyun bool osc_in_cmos_neg_inp_en; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* PLL1 Setting */ 161*4882a593Smuzhiyun unsigned short refa_r_div; 162*4882a593Smuzhiyun unsigned short refb_r_div; 163*4882a593Smuzhiyun unsigned short pll1_feedback_div; 164*4882a593Smuzhiyun unsigned short pll1_charge_pump_current_nA; 165*4882a593Smuzhiyun bool zero_delay_mode_internal_en; 166*4882a593Smuzhiyun bool osc_in_feedback_en; 167*4882a593Smuzhiyun enum pll1_rzero_resistor pll1_loop_filter_rzero; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* Reference */ 170*4882a593Smuzhiyun enum ref_sel_mode ref_mode; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* PLL2 Setting */ 173*4882a593Smuzhiyun unsigned int pll2_charge_pump_current_nA; 174*4882a593Smuzhiyun unsigned char pll2_ndiv_a_cnt; 175*4882a593Smuzhiyun unsigned char pll2_ndiv_b_cnt; 176*4882a593Smuzhiyun bool pll2_freq_doubler_en; 177*4882a593Smuzhiyun unsigned char pll2_r2_div; 178*4882a593Smuzhiyun unsigned char pll2_vco_div_m1; /* 3..5 */ 179*4882a593Smuzhiyun unsigned char pll2_vco_div_m2; /* 3..5 */ 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* Loop Filter PLL2 */ 182*4882a593Smuzhiyun enum rpole2_resistor rpole2; 183*4882a593Smuzhiyun enum rzero_resistor rzero; 184*4882a593Smuzhiyun enum cpole1_capacitor cpole1; 185*4882a593Smuzhiyun bool rzero_bypass_en; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* Output Channel Configuration */ 188*4882a593Smuzhiyun int num_channels; 189*4882a593Smuzhiyun struct ad9523_channel_spec *channels; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun char name[SPI_NAME_SIZE]; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun #endif /* IIO_FREQUENCY_AD9523_H_ */ 195