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/OK3568_Linux_fs/kernel/arch/arm/mach-sa1100/
H A Dpci-nanoengine.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-sa1100/pci-nanoengine.c
7 * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
14 #include <asm/mach-types.h>
22 if (bus->number != 0 || (devfn >> 3) != 0) in nanoengine_pci_map_bus()
26 ((bus->number << 16) | (devfn << 8) | (where & ~3)); in nanoengine_pci_map_bus()
45 .name = "PCI non-prefetchable",
49 .end = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
50 /* .end = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/
55 * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2080a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57";
20 cpu-idle-states = <&CPU_PW20>;
21 next-level-cache = <&cluster0_l2>;
22 #cooling-cells = <2>;
27 compatible = "arm,cortex-a57";
30 cpu-idle-states = <&CPU_PW20>;
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H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dv3-v360epc-pci.txt6 - compatible: should be one of:
7 "v3,v360epc-pci"
8 "arm,integrator-ap-pci", "v3,v360epc-pci"
9 - reg: should contain two register areas:
12 - interrupts: should contain a reference to the V3 error interrupt
14 - bus-range: see pci.txt
15 - ranges: this follows the standard PCI bindings in the IEEE Std
16 1275-1994 (see pci.txt) with the following restriction:
17 - The non-prefetchable and prefetchable memory windows must
19 - The prefetchable memory window must be immediately adjacent
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H A Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
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H A Dnvidia,tegra194-pcie.txt4 and thus inherits all the common properties defined in designware-pcie.txt.
9 - power-domains: A phandle to the node that controls power to the respective
19 "include/dt-bindings/power/tegra194-powergate.h" file.
20 - reg: A list of physical base address and length pairs for each set of
21 controller registers. Must contain an entry for each entry in the reg-names
23 - reg-names: Must include the following entries:
25 "config": As per the definition in designware-pcie.txt
31 - interrupts: A list of interrupt outputs of the controller. Must contain an
32 entry for each entry in the interrupt-names property.
33 - interrupt-names: Must include the following entries:
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H A Dversatile.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 - $ref: /schemas/pci/pci-bus.yaml#
20 const: arm,versatile-pci
24 - description: Versatile-specific registers
25 - description: Self Config space
26 - description: Config space
31 "#interrupt-cells": true
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H A Dxilinx-nwl-pcie.txt4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
21 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
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H A Dlayerscape-pci.txt4 and thus inherits all the common properties defined in designware-pcie.txt.
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
22 "fsl,ls1043a-pcie"
23 "fsl,ls1012a-pcie"
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H A Dfaraday,ftpci100.txt14 - compatible: ranging from specific to generic, should be one of
15 "cortina,gemini-pci", "faraday,ftpci100"
16 "cortina,gemini-pci-dual", "faraday,ftpci100-dual"
18 "faraday,ftpci100-dual"
19 - reg: memory base and size for the host bridge
20 - #address-cells: set to <3>
21 - #size-cells: set to <2>
22 - #interrupt-cells: set to <1>
23 - bus-range: set to <0x00 0xff>
24 - device_type, set to "pci"
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H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
41 - description:
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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dfsl-ls2080a.dtsi4 * Copyright 2013-2015 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
18 /* DRAM space - 1, size : 2 GB DRAM */
21 gic: interrupt-controller@6000000 {
22 compatible = "arm,gic-v3";
25 #interrupt-cells = <3>;
26 interrupt-controller;
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H A Dfsl-ls1043a.dtsi2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * Copyright (C) 2014-2015, Freescale Semiconductor
17 interrupt-parent = <&gic>;
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <100000000>;
23 clock-output-names = "sysclk";
26 gic: interrupt-controller@1400000 {
27 compatible = "arm,gic-400";
28 #interrupt-cells = <3>;
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H A Dfsl-ls1046a.dtsi2 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
17 interrupt-parent = <&gic>;
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <100000000>;
23 clock-output-names = "sysclk";
26 gic: interrupt-controller@1400000 {
27 compatible = "arm,gic-400";
28 #interrupt-cells = <3>;
29 interrupt-controller;
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H A Darmada-cp110-slave.dtsi4 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/comphy/comphy_data.h>
50 cp110-slave {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
57 config-space {
58 #address-cells = <1>;
59 #size-cells = <1>;
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H A Darmada-cp110-master.dtsi4 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/comphy/comphy_data.h>
50 cp110-master {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
57 config-space {
58 #address-cells = <1>;
59 #size-cells = <1>;
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/OK3568_Linux_fs/kernel/drivers/pci/
H A Dsetup-bus.c1 // SPDX-License-Identifier: GPL-2.0
11 * PCI-PCI bridges cleanup, sorted resource allocation.
14 * tighter packing. Prefetchable range support.
47 list_del(&dev_res->list); in free_list()
53 * add_to_list() - Add a new resource tracker to the list
68 return -ENOMEM; in add_to_list()
70 tmp->res = res; in add_to_list()
71 tmp->dev = dev; in add_to_list()
72 tmp->start = res->start; in add_to_list()
73 tmp->end = res->end; in add_to_list()
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H A Dsetup-res.c1 // SPDX-License-Identifier: GPL-2.0
32 struct resource *res = dev->resource + resno; in pci_std_update_resource()
34 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ in pci_std_update_resource()
35 if (dev->is_virtfn) in pci_std_update_resource()
42 if (!res->flags) in pci_std_update_resource()
45 if (res->flags & IORESOURCE_UNSET) in pci_std_update_resource()
49 * Ignore non-moveable resources. This might be legacy resources for in pci_std_update_resource()
53 if (res->flags & IORESOURCE_PCI_FIXED) in pci_std_update_resource()
56 pcibios_resource_to_bus(dev->bus, &region, res); in pci_std_update_resource()
59 if (res->flags & IORESOURCE_IO) { in pci_std_update_resource()
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/OK3568_Linux_fs/kernel/drivers/pci/controller/
H A Dpci-v3-semi.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on the code from arch/arm/mach-integrator/pci_v3.c
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
136 /* PCI BASE bits (PCI -> Local Bus) */
143 /* PCI MAP bits (PCI -> Local bus) */
152 /* LB_BASE0,1 bits (Local bus -> PCI) */
174 /* LB_MAP0,1 bits (Local bus -> PCI) */
187 /* LB_BASE2 bits (Local bus -> PCI IO) */
194 /* LB_MAP2 bits (Local bus -> PCI IO) */
231 /* ARM Integrator-specific extended control registers */
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/OK3568_Linux_fs/u-boot/board/armltd/integrator/
H A Dpci.c3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
21 * SPDX-License-Identifier: GPL-2.0+
26 #include "integrator-sc.h"
34 * where we read and write stuff - you don't want to try to
47 * range that devices actually use - what would they be doing at
107 * Linux calls the thing U-Boot calls "DEV" "SLOT" in v3_open_config_window()
115 * build the PCI configuration "address" with one-hot in in v3_open_config_window()
116 * A31-A11 in v3_open_config_window()
129 mapaddress |= 1 << (slot - 5); in v3_open_config_window()
154 * prefetchable), this frees up base1 for re-use by in v3_open_config_window()
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
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H A Dversatile-pb.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "versatile-ab.dts"
6 compatible = "arm,versatile-pb";
10 sic: interrupt-controller@10003000 {
11 clear-mask = <0xffffffff>;
14 * figure 3-30 page 3-74 of ARM DUI 0224B
16 valid-mask = <0x7fe003ff>;
23 gpio-controller;
24 #gpio-cells = <2>;
25 interrupt-controller;
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/OK3568_Linux_fs/kernel/arch/x86/pci/
H A Dbroadcom_bus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <asm/pci-direct.h>
45 /* read the non-prefetchable memory window */ in cnb20le_res()
55 /* read the prefetchable memory window */ in cnb20le_res()
81 list_for_each_entry(root_res, &info->resources, list) in cnb20le_res()
82 printk(KERN_INFO "host bridge window %pR\n", &root_res->res); in cnb20le_res()
/OK3568_Linux_fs/kernel/arch/powerpc/boot/
H A Dcuboot-pq2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Old U-boot compatibility for PowerQUICC II
15 #include "fsl-soc.h"
40 /* Different versions of u-boot put the BCSR in different places, and
44 * For any node defined as compatible with fsl,pq2-localbus,
58 if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-localbus")) in update_cs_ranges()
103 option | ~(cs_ranges_buf[i].size - 1)); in update_cs_ranges()
113 /* Older u-boots don't set PCI up properly. Update the hardware to match
114 * the device tree. The prefetch mem region and non-prefetch mem region
117 * 32-bit PCI is supported. All three region types (prefetchable mem,
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/OK3568_Linux_fs/kernel/arch/arm/mach-cns3xxx/
H A Dpcie.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCI-E support for CNS3xxx
38 return root->private_data; in sysdata_to_cnspci()
43 return sysdata_to_cnspci(dev->sysdata); in pdev_to_cnspci()
48 return sysdata_to_cnspci(bus->sysdata); in pbus_to_cnspci()
55 int busno = bus->number; in cns3xxx_pci_map_bus()
60 if (!cnspci->linked && busno > 0) in cns3xxx_pci_map_bus()
71 base = cnspci->host_regs; in cns3xxx_pci_map_bus()
77 base = cnspci->cfg0_regs; in cns3xxx_pci_map_bus()
81 base = cnspci->cfg1_regs + ((busno & 0xf) << 20); in cns3xxx_pci_map_bus()
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