1*4882a593SmuzhiyunFreescale Layerscape PCIe controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis PCIe host controller is based on the Synopsys DesignWare PCIe IP 4*4882a593Smuzhiyunand thus inherits all the common properties defined in designware-pcie.txt. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThis controller derives its clocks from the Reset Configuration Word (RCW) 7*4882a593Smuzhiyunwhich is used to describe the PLL settings at the time of chip-reset. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunAlso as per the available Reference Manuals, there is no specific 'version' 10*4882a593Smuzhiyunregister available in the Freescale PCIe controller register set, 11*4882a593Smuzhiyunwhich can allow determining the underlying DesignWare PCIe controller version 12*4882a593Smuzhiyuninformation. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRequired properties: 15*4882a593Smuzhiyun- compatible: should contain the platform identifier such as: 16*4882a593Smuzhiyun RC mode: 17*4882a593Smuzhiyun "fsl,ls1021a-pcie" 18*4882a593Smuzhiyun "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" 19*4882a593Smuzhiyun "fsl,ls2088a-pcie" 20*4882a593Smuzhiyun "fsl,ls1088a-pcie" 21*4882a593Smuzhiyun "fsl,ls1046a-pcie" 22*4882a593Smuzhiyun "fsl,ls1043a-pcie" 23*4882a593Smuzhiyun "fsl,ls1012a-pcie" 24*4882a593Smuzhiyun "fsl,ls1028a-pcie" 25*4882a593Smuzhiyun EP mode: 26*4882a593Smuzhiyun "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" 27*4882a593Smuzhiyun "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep" 28*4882a593Smuzhiyun "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep" 29*4882a593Smuzhiyun- reg: base addresses and lengths of the PCIe controller register blocks. 30*4882a593Smuzhiyun- interrupts: A list of interrupt outputs of the controller. Must contain an 31*4882a593Smuzhiyun entry for each entry in the interrupt-names property. 32*4882a593Smuzhiyun- interrupt-names: Must include the following entries: 33*4882a593Smuzhiyun "intr": The interrupt that is asserted for controller interrupts 34*4882a593Smuzhiyun- fsl,pcie-scfg: Must include two entries. 35*4882a593Smuzhiyun The first entry must be a link to the SCFG device node 36*4882a593Smuzhiyun The second entry must be '0' or '1' based on physical PCIe controller index. 37*4882a593Smuzhiyun This is used to get SCFG PEXN registers 38*4882a593Smuzhiyun- dma-coherent: Indicates that the hardware IP block can ensure the coherency 39*4882a593Smuzhiyun of the data transferred from/to the IP block. This can avoid the software 40*4882a593Smuzhiyun cache flush/invalid actions, and improve the performance significantly. 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunExample: 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun pcie@3400000 { 45*4882a593Smuzhiyun compatible = "fsl,ls1021a-pcie"; 46*4882a593Smuzhiyun reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 47*4882a593Smuzhiyun 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 48*4882a593Smuzhiyun reg-names = "regs", "config"; 49*4882a593Smuzhiyun interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 50*4882a593Smuzhiyun interrupt-names = "intr"; 51*4882a593Smuzhiyun fsl,pcie-scfg = <&scfg 0>; 52*4882a593Smuzhiyun #address-cells = <3>; 53*4882a593Smuzhiyun #size-cells = <2>; 54*4882a593Smuzhiyun device_type = "pci"; 55*4882a593Smuzhiyun dma-coherent; 56*4882a593Smuzhiyun num-lanes = <4>; 57*4882a593Smuzhiyun bus-range = <0x0 0xff>; 58*4882a593Smuzhiyun ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 59*4882a593Smuzhiyun 0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */ 60*4882a593Smuzhiyun 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 61*4882a593Smuzhiyun #interrupt-cells = <1>; 62*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 7>; 63*4882a593Smuzhiyun interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 64*4882a593Smuzhiyun <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 65*4882a593Smuzhiyun <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 66*4882a593Smuzhiyun <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 67*4882a593Smuzhiyun }; 68