1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pci/versatile.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: ARM Versatile Platform Baseboard PCI interface 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Rob Herring <robh@kernel.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: |+ 13*4882a593Smuzhiyun PCI host controller found on the ARM Versatile PB board's FPGA. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunallOf: 16*4882a593Smuzhiyun - $ref: /schemas/pci/pci-bus.yaml# 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunproperties: 19*4882a593Smuzhiyun compatible: 20*4882a593Smuzhiyun const: arm,versatile-pci 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun reg: 23*4882a593Smuzhiyun items: 24*4882a593Smuzhiyun - description: Versatile-specific registers 25*4882a593Smuzhiyun - description: Self Config space 26*4882a593Smuzhiyun - description: Config space 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun ranges: 29*4882a593Smuzhiyun maxItems: 3 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun "#interrupt-cells": true 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun interrupt-map: 34*4882a593Smuzhiyun maxItems: 16 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun interrupt-map-mask: 37*4882a593Smuzhiyun items: 38*4882a593Smuzhiyun - const: 0x1800 39*4882a593Smuzhiyun - const: 0 40*4882a593Smuzhiyun - const: 0 41*4882a593Smuzhiyun - const: 7 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunrequired: 44*4882a593Smuzhiyun - compatible 45*4882a593Smuzhiyun - reg 46*4882a593Smuzhiyun - ranges 47*4882a593Smuzhiyun - "#interrupt-cells" 48*4882a593Smuzhiyun - interrupt-map 49*4882a593Smuzhiyun - interrupt-map-mask 50*4882a593Smuzhiyun 51*4882a593SmuzhiyununevaluatedProperties: false 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunexamples: 54*4882a593Smuzhiyun - | 55*4882a593Smuzhiyun pci@10001000 { 56*4882a593Smuzhiyun compatible = "arm,versatile-pci"; 57*4882a593Smuzhiyun device_type = "pci"; 58*4882a593Smuzhiyun reg = <0x10001000 0x1000>, 59*4882a593Smuzhiyun <0x41000000 0x10000>, 60*4882a593Smuzhiyun <0x42000000 0x100000>; 61*4882a593Smuzhiyun bus-range = <0 0xff>; 62*4882a593Smuzhiyun #address-cells = <3>; 63*4882a593Smuzhiyun #size-cells = <2>; 64*4882a593Smuzhiyun #interrupt-cells = <1>; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun ranges = 67*4882a593Smuzhiyun <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */ 68*4882a593Smuzhiyun <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */ 69*4882a593Smuzhiyun <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun interrupt-map-mask = <0x1800 0 0 7>; 72*4882a593Smuzhiyun interrupt-map = <0x1800 0 0 1 &sic 28>, 73*4882a593Smuzhiyun <0x1800 0 0 2 &sic 29>, 74*4882a593Smuzhiyun <0x1800 0 0 3 &sic 30>, 75*4882a593Smuzhiyun <0x1800 0 0 4 &sic 27>, 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun <0x1000 0 0 1 &sic 27>, 78*4882a593Smuzhiyun <0x1000 0 0 2 &sic 28>, 79*4882a593Smuzhiyun <0x1000 0 0 3 &sic 29>, 80*4882a593Smuzhiyun <0x1000 0 0 4 &sic 30>, 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun <0x0800 0 0 1 &sic 30>, 83*4882a593Smuzhiyun <0x0800 0 0 2 &sic 27>, 84*4882a593Smuzhiyun <0x0800 0 0 3 &sic 28>, 85*4882a593Smuzhiyun <0x0800 0 0 4 &sic 29>, 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun <0x0000 0 0 1 &sic 29>, 88*4882a593Smuzhiyun <0x0000 0 0 2 &sic 30>, 89*4882a593Smuzhiyun <0x0000 0 0 3 &sic 27>, 90*4882a593Smuzhiyun <0x0000 0 0 4 &sic 28>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun... 95