arm/dts/fsl-ls1043a.dtsi

2  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4  * Copyright (C) 2014-2015, Freescale Semiconductor
17 	interrupt-parent = <&gic>;
20 		compatible = "fixed-clock";
21 		#clock-cells = <0>;
22 		clock-frequency = <100000000>;
23 		clock-output-names = "sysclk";
26 	gic: interrupt-controller@1400000 {
27 		compatible = "arm,gic-400";
28 		#interrupt-cells = <3>;
29 		interrupt-controller;
38 		compatible = "simple-bus";
39 		#address-cells = <2>;
40 		#size-cells = <2>;
44 			compatible = "fsl,ls1043a-clockgen";
46 			#clock-cells = <2>;
51 			compatible = "fsl,vf610-dspi";
52 			#address-cells = <1>;
53 			#size-cells = <0>;
56 			clock-names = "dspi";
58 			num-cs = <6>;
59 			big-endian;
64 			compatible = "fsl,vf610-dspi";
65 			#address-cells = <1>;
66 			#size-cells = <0>;
69 			clock-names = "dspi";
71 			num-cs = <6>;
72 			big-endian;
77 			compatible = "fsl,ifc", "simple-bus";
83 			compatible = "fsl,vf610-i2c";
84 			#address-cells = <1>;
85 			#size-cells = <0>;
88 			clock-names = "i2c";
94 			compatible = "fsl,vf610-i2c";
95 			#address-cells = <1>;
96 			#size-cells = <0>;
99 			clock-names = "i2c";
105 			compatible = "fsl,vf610-i2c";
106 			#address-cells = <1>;
107 			#size-cells = <0>;
110 			clock-names = "i2c";
116 			compatible = "fsl,vf610-i2c";
117 			#address-cells = <1>;
118 			#size-cells = <0>;
121 			clock-names = "i2c";
155 			compatible = "fsl,ls1021a-lpuart";
159 			clock-names = "ipg";
164 			compatible = "fsl,ls1021a-lpuart";
168 			clock-names = "ipg";
173 			compatible = "fsl,ls1021a-lpuart";
176 			clock-names = "ipg";
182 			compatible = "fsl,ls1021a-lpuart";
186 			clock-names = "ipg";
191 			compatible = "fsl,ls1021a-lpuart";
195 			clock-names = "ipg";
200 			compatible = "fsl,ls1021a-lpuart";
204 			clock-names = "ipg";
208 			compatible = "fsl,vf610-qspi";
209 			#address-cells = <1>;
210 			#size-cells = <0>;
213 			reg-names = "QuadSPI", "QuadSPI-memory";
214 			num-cs = <2>;
215 			big-endian;
220 			compatible = "fsl,layerscape-dwc3";
227 			compatible = "fsl,layerscape-dwc3";
234 			compatible = "fsl,layerscape-dwc3";
241 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
245 			reg-names = "dbi", "lut", "config";
246 			big-endian;
247 			#address-cells = <3>;
248 			#size-cells = <2>;
250 			bus-range = <0x0 0xff>;
252 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
256 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
260 			reg-names = "dbi", "lut", "config";
261 			big-endian;
262 			#address-cells = <3>;
263 			#size-cells = <2>;
265 			num-lanes = <2>;
266 			bus-range = <0x0 0xff>;
268 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
272 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
276 			reg-names = "dbi", "lut", "config";
277 			big-endian;
278 			#address-cells = <3>;
279 			#size-cells = <2>;
281 			bus-range = <0x0 0xff>;
283 				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */