| /OK3568_Linux_fs/kernel/drivers/clk/meson/ |
| H A D | clk-mpll.c | 9 * scaling capabilities. MPLL rates are calculated as:
19 #include "clk-mpll.h"
79 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); in mpll_recalc_rate() local
83 sdm = meson_parm_read(clk->map, &mpll->sdm); in mpll_recalc_rate()
84 n2 = meson_parm_read(clk->map, &mpll->n2); in mpll_recalc_rate()
95 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); in mpll_round_rate() local
98 params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags); in mpll_round_rate()
107 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); in mpll_set_rate() local
111 params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags); in mpll_set_rate()
113 if (mpll->lock) in mpll_set_rate()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/ |
| H A D | radeon_clocks.c | 72 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_legacy_get_memory_clock() local
78 fb_div *= mpll->reference_freq; in radeon_legacy_get_memory_clock()
112 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_read_clocks_OF() local
150 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
151 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
187 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_get_clock_info() local
219 if (mpll->reference_div < 2) in radeon_get_clock_info()
220 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
234 mpll->reference_freq = 1432; in radeon_get_clock_info()
239 mpll->reference_freq = 2700; in radeon_get_clock_info()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/clk/samsung/ |
| H A D | clk-s3c2410.c | 35 mpll, upll, enumerator
54 PNAME(fclk_p) = { "mpll", "div_slow" };
109 ALIAS(MPLL, NULL, "mpll"),
155 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
162 DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
221 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
342 s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl; in s3c2410_common_clk_init()
356 s3c244x_common_plls[mpll].rate_table = in s3c2410_common_clk_init()
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| H A D | clk-s3c2412.c | 80 PNAME(i2sclk_p) = { "erefclk", "mpll" };
81 PNAME(uartclk_p) = { "erefclk", "mpll" };
83 PNAME(msysclk_p) = { "mdivclk", "mpll" };
101 PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
155 ALIAS(MPLL, NULL, "mpll"),
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| H A D | clk-s3c2443.c | 66 PNAME(msysclk_p) = { "mpllref", "mpll" };
148 ALIAS(MPLL, NULL, "mpll"),
182 PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
234 PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
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| H A D | clk-s3c2410-dclk.c | 146 static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
148 static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
151 static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
158 static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_atomfirmware.c | 381 struct amdgpu_pll *mpll = &adev->clock.mpll; in amdgpu_atomfirmware_get_clock_info() local
441 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
443 mpll->reference_div = 0; in amdgpu_atomfirmware_get_clock_info()
444 mpll->min_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
445 mpll->max_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
446 mpll->min_ref_div = 2; in amdgpu_atomfirmware_get_clock_info()
447 mpll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
448 mpll->min_feedback_div = 4; in amdgpu_atomfirmware_get_clock_info()
449 mpll->max_feedback_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
450 mpll->best_vco = 0; in amdgpu_atomfirmware_get_clock_info()
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| H A D | amdgpu_atombios.c | 571 struct amdgpu_pll *mpll = &adev->clock.mpll; in amdgpu_atombios_get_clock_info() local
643 mpll->reference_freq = in amdgpu_atombios_get_clock_info()
645 mpll->reference_div = 0; in amdgpu_atombios_get_clock_info()
647 mpll->pll_out_min = in amdgpu_atombios_get_clock_info()
649 mpll->pll_out_max = in amdgpu_atombios_get_clock_info()
653 if (mpll->pll_out_min == 0) in amdgpu_atombios_get_clock_info()
654 mpll->pll_out_min = 64800; in amdgpu_atombios_get_clock_info()
656 mpll->pll_in_min = in amdgpu_atombios_get_clock_info()
658 mpll->pll_in_max = in amdgpu_atombios_get_clock_info()
666 mpll->min_post_div = 1; in amdgpu_atombios_get_clock_info()
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/ |
| H A D | clock.c | 126 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || in exynos_get_pll_clk()
196 case MPLL: in exynos4_get_pll_clk()
226 case MPLL: in exynos4x12_get_pll_clk()
257 case MPLL: in exynos5_get_pll_clk()
278 /* According to the user manual, in EVT1 MPLL and BPLL always gives in exynos5_get_pll_clk()
279 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ in exynos5_get_pll_clk()
280 if (pllreg == MPLL || pllreg == BPLL) { in exynos5_get_pll_clk()
284 case MPLL: in exynos5_get_pll_clk()
315 case MPLL: in exynos542x_get_pll_clk()
438 sclk = exynos5_get_pll_clk(MPLL); in exynos5_get_periph_rate()
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-s5pc1xx/ |
| H A D | clock.c | 37 case MPLL: in s5pc100_get_pll_clk()
88 case MPLL: in s5pc110_get_pll_clk()
108 if (pllreg == APLL || pllreg == MPLL) in s5pc110_get_pll_clk()
207 d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1); in get_pclkd1()
237 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1); in get_hclk_sys()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| H A D | nv04.c | 288 bool mpll = Preg == 0x4020; in setPLL_double_lowregs() local
291 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | in setPLL_double_lowregs()
306 if (mpll) { in setPLL_double_lowregs()
322 Pval |= mpll ? 1 << 12 : 1 << 8; in setPLL_double_lowregs()
326 if (mpll) { in setPLL_double_lowregs()
340 if (mpll) { in setPLL_double_lowregs()
349 if (mpll) { in setPLL_double_lowregs()
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| /OK3568_Linux_fs/kernel/drivers/phy/qualcomm/ |
| H A D | phy-qcom-ipq806x-usb.c | 61 /* Override value for mpll */
104 /* MPLL bits */
121 u32 mpll; member
410 data |= SSPHY_MPLL(phy_dwc3->mpll); in qcom_ipq806x_usb_ss_phy_init()
536 if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll)) in qcom_ipq806x_usb_phy_probe()
537 phy_dwc3->mpll = SSPHY_MPLL_VALUE; in qcom_ipq806x_usb_phy_probe()
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| /OK3568_Linux_fs/kernel/drivers/clk/uniphier/ |
| H A D | clk-uniphier-sys.c | 187 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */
206 UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
213 "mpll/2", "spll/4", "mpll/3", "spll/3",
214 "spll/4", "spll/8", "mpll/4", "mpll/8"),
221 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */
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| /OK3568_Linux_fs/kernel/drivers/clk/imx/ |
| H A D | clk-imx35.c | 65 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
109 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
112 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); in _mx35_clocks_init()
117 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); in _mx35_clocks_init()
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| H A D | clk-imx27.c | 35 static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
40 "ckih_gate", "mpll", "spll", "cpu_div",
47 static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
64 clk[IMX27_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "mpll", "mpll_sel", CCM_MPCTL0); in _mx27_clocks_init()
67 clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); in _mx27_clocks_init()
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| H A D | clk-imx31.c | 34 static const char *mcu_main_sel[] = { "spll", "mpll", };
40 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
69 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); in _mx31_clocks_init()
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| H A D | clk-imx25.c | 45 static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
53 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
81 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
83 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); in __mx25_clocks_init()
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| H A D | clk-imx1.c | 47 clk[IMX1_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "mpll", "clk32_premult", CCM_MPCTL0); in mx1_clocks_init_dt()
48 clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); in mx1_clocks_init_dt()
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| /OK3568_Linux_fs/u-boot/board/samsung/odroid/ |
| H A D | odroid.c | 101 * CMU_CPU clocks src to MPLL in board_clock_init()
184 * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI) in board_clock_init()
203 /* Set MPLL to 800MHz */ in board_clock_init()
274 * Set CLK_SRC_PERIL0 clocks src to MPLL in board_clock_init()
306 * For MOUTmmc0-3 = 800 MHz (MPLL) in board_clock_init()
326 * For MOUTmmc0-3 = 800 MHz (MPLL) in board_clock_init()
345 * For MOUTmmc4 = 800 MHz (MPLL) in board_clock_init()
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| /OK3568_Linux_fs/kernel/drivers/clk/mvebu/ |
| H A D | mv98dx3236.c | 24 * SAR1[20:18] : CPU frequency DDR frequency MPLL frequency
33 * SAR1[20:18] : CPU frequency DDR frequency MPLL frequency
94 { .id = MV98DX3236_CPU_TO_MPLL, .name = "mpll" },
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/ |
| H A D | qcom,ipq806x-usb-phy-ss.yaml | 50 qcom,mpll:
52 description: Override value for mpll.
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| /OK3568_Linux_fs/kernel/arch/arm/mach-s3c/ |
| H A D | cpufreq-utils-s3c24xx.c | 60 if (!IS_ERR(cfg->mpll)) in s3c2410_set_fvco()
61 clk_set_rate(cfg->mpll, cfg->pll.frequency); in s3c2410_set_fvco()
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/sprd/ |
| H A D | sharkl3.dtsi | 91 mpll: mpll { label
92 compatible = "sprd,sc9863a-mpll";
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| /OK3568_Linux_fs/u-boot/arch/mips/mach-pic32/ |
| H A D | cpu.c | 158 printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL))); in soc_clk_dump()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ |
| H A D | mvebu-core-clock.txt | 38 3 = mpll (MPLL Clock)
|