Lines Matching full:mpll
126 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || in exynos_get_pll_clk()
196 case MPLL: in exynos4_get_pll_clk()
226 case MPLL: in exynos4x12_get_pll_clk()
257 case MPLL: in exynos5_get_pll_clk()
278 /* According to the user manual, in EVT1 MPLL and BPLL always gives in exynos5_get_pll_clk()
279 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ in exynos5_get_pll_clk()
280 if (pllreg == MPLL || pllreg == BPLL) { in exynos5_get_pll_clk()
284 case MPLL: in exynos5_get_pll_clk()
315 case MPLL: in exynos542x_get_pll_clk()
438 sclk = exynos5_get_pll_clk(MPLL); in exynos5_get_periph_rate()
529 sclk = exynos542x_get_pll_clk(MPLL); in exynos542x_get_periph_rate()
653 sclk = get_pll_clk(MPLL); in exynos4_get_pwm_clk()
668 sclk = get_pll_clk(MPLL); in exynos4_get_pwm_clk()
684 sclk = get_pll_clk(MPLL); in exynos4x12_get_pwm_clk()
714 sclk = get_pll_clk(MPLL); in exynos4_get_uart_clk()
760 sclk = get_pll_clk(MPLL); in exynos4x12_get_uart_clk()
796 sclk = get_pll_clk(MPLL); in exynos4_get_mmc_clk()
934 sclk = get_pll_clk(MPLL); in exynos4_get_lcd_clk()
976 sclk = get_pll_clk(MPLL); in exynos5_get_lcd_clk()
1050 const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, in exynos5800_get_lcd_clk()