Home
last modified time | relevance | path

Searched full:esdhc (Results 1 – 25 of 758) sorted by relevance

12345678910>>...31

/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-of-esdhc.c3 * Freescale eSDHC controller driver.
27 #include "sdhci-esdhc.h"
65 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
66 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
67 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
68 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
69 { .compatible = "fsl,mpc8379-esdhc" },
70 { .compatible = "fsl,mpc8536-esdhc" },
71 { .compatible = "fsl,esdhc" },
94 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
[all …]
H A Dsdhci-esdhc-mcf.c3 * Freescale eSDHC ColdFire family controller driver, platform bus.
11 #include <linux/platform_data/mmc-esdhc-mcf.h>
14 #include "sdhci-esdhc.h"
21 * Freescale eSDHC has DMA ERR flag at bit 28, not as std spec says, bit 25.
235 * ColdFire eSDHC clock.s in esdhc_mcf_pltfm_set_clock()
238 * +-> / outdiv3 --> eSDHC clock ---> / SDCCLKFS / DVS in esdhc_mcf_pltfm_set_clock()
241 * (8.1.2) eSDHC should be 40 MHz max in esdhc_mcf_pltfm_set_clock()
242 * (25.3.9) eSDHC input is, as example, 96 Mhz ... in esdhc_mcf_pltfm_set_clock()
511 .name = "sdhci-esdhc-mcf",
520 MODULE_DESCRIPTION("SDHCI driver for Freescale ColdFire eSDHC");
H A Dsdhci-pltfm.c66 if (of_device_is_compatible(np, "fsl,p2020-rev1-esdhc")) in sdhci_get_compatibility()
69 if (of_device_is_compatible(np, "fsl,p2020-esdhc") || in sdhci_get_compatibility()
70 of_device_is_compatible(np, "fsl,p1010-esdhc") || in sdhci_get_compatibility()
71 of_device_is_compatible(np, "fsl,t4240-esdhc") || in sdhci_get_compatibility()
72 of_device_is_compatible(np, "fsl,mpc8536-esdhc")) in sdhci_get_compatibility()
H A Dsdhci-esdhc-imx.c3 * Freescale eSDHC i.MX controller driver for the platform bus.
27 #include <linux/platform_data/mmc-esdhc-imx.h>
31 #include "sdhci-esdhc.h"
121 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
122 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
123 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
124 * Define this macro DMA error INT for fsl eSDHC
144 * The flag tells that the ESDHC controller is an USDHC block that is
299 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
300 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
[all …]
H A Dsdhci-esdhc.h3 * Freescale eSDHC controller driver generics for OF and pltfm.
16 * Ops and quirks for the Freescale eSDHC controller.
30 * eSDHC register definition
H A DMakefile88 obj-$(CONFIG_MMC_SDHCI_ESDHC_MCF) += sdhci-esdhc-mcf.o
89 obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
95 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dfsl-esdhc.txt1 * Freescale Enhanced Secure Digital Host Controller (eSDHC)
7 by mmc.txt and the properties used by the sdhci-esdhc driver.
10 - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
12 "fsl,mpc8536-esdhc"
13 "fsl,mpc8378-esdhc"
14 "fsl,p2020-esdhc"
15 "fsl,p4080-esdhc"
16 "fsl,t1040-esdhc"
17 "fsl,t4240-esdhc"
19 "fsl,ls1012a-esdhc"
[all …]
H A Dfsl-imx-esdhc.yaml4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
28 - fsl,imx51-esdhc
29 - fsl,imx53-esdhc
62 due to signal path is too long on the board. Please refer to eSDHC/uSDHC
115 compatible = "fsl,imx51-esdhc";
122 compatible = "fsl,imx51-esdhc";
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.fsl-esdhc1 Freescale esdhc-specific options
18 ESDHC IP is in little-endian mode. Accessing ESDHC registers can be
19 determined by ESDHC IP's endian mode or processor's endian mode.
21 ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
22 by ESDHC IP's endian mode or processor's endian mode.
/OK3568_Linux_fs/u-boot/board/freescale/mpc8569mds/
H A Dmpc8569mds.c330 * Because of an erratum in prototype boards it is impossible to use eSDHC
332 * by simply issung 'setenv hwconfig esdhc', and not able to interact with
350 hwconfig_subarg_cmp("esdhc", "mode", "4-bits"); in esdhc_disables_uart0()
365 if (hwconfig("esdhc") && esdhc_disables_uart0()) { in fdt_board_fixup_qe_uart()
366 printf("QE UART: won't enable with esdhc.\n"); in fdt_board_fixup_qe_uart()
406 if (!hwconfig("esdhc")) in board_mmc_init()
409 printf("Enabling eSDHC...\n" in board_mmc_init()
410 " For eSDHC to function, I2C2 "); in board_mmc_init()
429 /* Assign I2C2 signals to eSDHC. */ in board_mmc_init()
435 /* Mux I2C2 (and optionally UART0) signals to eSDHC. */ in board_mmc_init()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx50.dtsi119 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
131 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
180 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
192 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dfsl-ls1012a.dtsi57 esdhc0: esdhc@1560000 {
58 compatible = "fsl,esdhc";
65 esdhc1: esdhc@1580000 {
66 compatible = "fsl,esdhc";
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dqoriq-esdhc-0.dtsi2 * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
36 compatible = "fsl,esdhc";
H A Dpq3-esdhc-0.dtsi2 * PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ]
36 compatible = "fsl,esdhc";
H A Dp1020si-post.dtsi154 /include/ "pq3-esdhc-0.dtsi"
156 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
H A Dc293si-post.dtsi113 /include/ "pq3-esdhc-0.dtsi"
115 compatible = "fsl,c293-esdhc", "fsl,esdhc";
H A Dp1010si-post.dtsi172 /include/ "pq3-esdhc-0.dtsi"
174 compatible = "fsl,p1010-esdhc", "fsl,esdhc";
H A Dp2020si-post.dtsi187 /include/ "pq3-esdhc-0.dtsi"
189 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
H A Dmpc8536si-post.dtsi238 /include/ "pq3-esdhc-0.dtsi"
240 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
H A Dp1022si-post.dtsi215 /include/ "pq3-esdhc-0.dtsi"
217 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi155 esdhc0: esdhc@1560000 {
156 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
173 esdhc1: esdhc@1580000 {
174 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dls102xa_devdis.h14 { "esdhc", 0x0, 0x20000000 }, /* eSDHC */
/OK3568_Linux_fs/u-boot/board/freescale/p1022ds/
H A Dtlb.c76 /* **** - eSDHC/eSPI/NAND boot */
80 /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
/OK3568_Linux_fs/kernel/arch/m68k/coldfire/
H A Dm5441x.c55 DEFINE_CLK(0, "sdhci-esdhc-mcf.0", 51, MCF_CLK);
163 &__clk_0_51, /* esdhc */
188 &__clk_0_51, /* eSDHC */
/OK3568_Linux_fs/u-boot/board/freescale/mpc8536ds/
H A DREADME48 The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC
50 initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from
64 For boot from eSDHC:

12345678910>>...31