1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __FSL_LS102XA_DEVDIS_H_ 8*4882a593Smuzhiyun #define __FSL_LS102XA_DEVDIS_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <fsl_devdis.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun const struct devdis_table devdis_tbl[] = { 13*4882a593Smuzhiyun { "pbl", 0x0, 0x80000000 }, /* PBL */ 14*4882a593Smuzhiyun { "esdhc", 0x0, 0x20000000 }, /* eSDHC */ 15*4882a593Smuzhiyun { "qdma", 0x0, 0x800000 }, /* qDMA */ 16*4882a593Smuzhiyun { "edma", 0x0, 0x400000 }, /* eDMA */ 17*4882a593Smuzhiyun { "usb3", 0x0, 0x84000 }, /* USB3.0 controller and PHY*/ 18*4882a593Smuzhiyun { "usb2", 0x0, 0x40000 }, /* USB2.0 controller */ 19*4882a593Smuzhiyun { "sata", 0x0, 0x8000 }, /* SATA */ 20*4882a593Smuzhiyun { "sec", 0x0, 0x200 }, /* SEC */ 21*4882a593Smuzhiyun { "dcu", 0x0, 0x2 }, /* Display controller Unit */ 22*4882a593Smuzhiyun { "qe", 0x0, 0x1 }, /* QUICC Engine */ 23*4882a593Smuzhiyun { "etsec1", 0x1, 0x80000000 }, /* eTSEC1 controller */ 24*4882a593Smuzhiyun { "etesc2", 0x1, 0x40000000 }, /* eTSEC2 controller */ 25*4882a593Smuzhiyun { "etsec3", 0x1, 0x20000000 }, /* eTSEC3 controller */ 26*4882a593Smuzhiyun { "pex1", 0x2, 0x80000000 }, /* PCIE controller 1 */ 27*4882a593Smuzhiyun { "pex2", 0x2, 0x40000000 }, /* PCIE controller 2 */ 28*4882a593Smuzhiyun { "duart1", 0x3, 0x20000000 }, /* DUART1 */ 29*4882a593Smuzhiyun { "duart2", 0x3, 0x10000000 }, /* DUART2 */ 30*4882a593Smuzhiyun { "qspi", 0x3, 0x8000000 }, /* QSPI */ 31*4882a593Smuzhiyun { "ddr", 0x4, 0x80000000 }, /* DDR */ 32*4882a593Smuzhiyun { "ocram1", 0x4, 0x8000000 }, /* OCRAM1 */ 33*4882a593Smuzhiyun { "ifc", 0x4, 0x800000 }, /* IFC */ 34*4882a593Smuzhiyun { "gpio", 0x4, 0x400000 }, /* GPIO */ 35*4882a593Smuzhiyun { "dbg", 0x4, 0x200000 }, /* DBG */ 36*4882a593Smuzhiyun { "can1", 0x4, 0x80000 }, /* FlexCAN1 */ 37*4882a593Smuzhiyun { "can2_4", 0x4, 0x40000 }, /* FlexCAN2_3_4 */ 38*4882a593Smuzhiyun { "ftm2_8", 0x4, 0x20000 }, /* FlexTimer2_3_4_5_6_7_8 */ 39*4882a593Smuzhiyun { "secmon", 0x4, 0x4000 }, /* Security Monitor */ 40*4882a593Smuzhiyun { "wdog1_2", 0x4, 0x400 }, /* WatchDog1_2 */ 41*4882a593Smuzhiyun { "i2c2_3", 0x4, 0x200 }, /* I2C2_3 */ 42*4882a593Smuzhiyun { "sai1_4", 0x4, 0x100 }, /* SAI1_2_3_4 */ 43*4882a593Smuzhiyun { "lpuart2_6", 0x4, 0x80 }, /* LPUART2_3_4_5_6 */ 44*4882a593Smuzhiyun { "dspi1_2", 0x4, 0x40 }, /* DSPI1_2 */ 45*4882a593Smuzhiyun { "asrc", 0x4, 0x20 }, /* ASRC */ 46*4882a593Smuzhiyun { "spdif", 0x4, 0x10 }, /* SPDIF */ 47*4882a593Smuzhiyun { "i2c1", 0x4, 0x4 }, /* I2C1 */ 48*4882a593Smuzhiyun { "lpuart1", 0x4, 0x2 }, /* LPUART1 */ 49*4882a593Smuzhiyun { "ftm1", 0x4, 0x1 }, /* FlexTimer1 */ 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #endif 53