1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * C293 Silicon/SoC Device Tree Source (post include) 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 7*4882a593Smuzhiyun * modification, are permitted provided that the following conditions are met: 8*4882a593Smuzhiyun * * Redistributions of source code must retain the above copyright 9*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer. 10*4882a593Smuzhiyun * * Redistributions in binary form must reproduce the above copyright 11*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in the 12*4882a593Smuzhiyun * documentation and/or other materials provided with the distribution. 13*4882a593Smuzhiyun * * Neither the name of Freescale Semiconductor nor the 14*4882a593Smuzhiyun * names of its contributors may be used to endorse or promote products 15*4882a593Smuzhiyun * derived from this software without specific prior written permission. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * ALTERNATIVELY, this software may be distributed under the terms of the 19*4882a593Smuzhiyun * GNU General Public License ("GPL") as published by the Free Software 20*4882a593Smuzhiyun * Foundation, either version 2 of that License or (at your option) any 21*4882a593Smuzhiyun * later version. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24*4882a593Smuzhiyun * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25*4882a593Smuzhiyun * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26*4882a593Smuzhiyun * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27*4882a593Smuzhiyun * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28*4882a593Smuzhiyun * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29*4882a593Smuzhiyun * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30*4882a593Smuzhiyun * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32*4882a593Smuzhiyun * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun&ifc { 36*4882a593Smuzhiyun #address-cells = <2>; 37*4882a593Smuzhiyun #size-cells = <1>; 38*4882a593Smuzhiyun compatible = "fsl,ifc", "simple-bus"; 39*4882a593Smuzhiyun interrupts = <19 2 0 0>; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun/* controller at 0xa000 */ 43*4882a593Smuzhiyun&pci0 { 44*4882a593Smuzhiyun compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie"; 45*4882a593Smuzhiyun device_type = "pci"; 46*4882a593Smuzhiyun #size-cells = <2>; 47*4882a593Smuzhiyun #address-cells = <3>; 48*4882a593Smuzhiyun bus-range = <0 255>; 49*4882a593Smuzhiyun clock-frequency = <33333333>; 50*4882a593Smuzhiyun interrupts = <16 2 0 0>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun pcie@0 { 53*4882a593Smuzhiyun reg = <0 0 0 0 0>; 54*4882a593Smuzhiyun #interrupt-cells = <1>; 55*4882a593Smuzhiyun #size-cells = <2>; 56*4882a593Smuzhiyun #address-cells = <3>; 57*4882a593Smuzhiyun device_type = "pci"; 58*4882a593Smuzhiyun interrupts = <16 2 0 0>; 59*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0 0 7>; 60*4882a593Smuzhiyun interrupt-map = < 61*4882a593Smuzhiyun /* IDSEL 0x0 */ 62*4882a593Smuzhiyun 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 63*4882a593Smuzhiyun 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 64*4882a593Smuzhiyun 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 65*4882a593Smuzhiyun 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 66*4882a593Smuzhiyun >; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun}; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun&soc { 71*4882a593Smuzhiyun #address-cells = <1>; 72*4882a593Smuzhiyun #size-cells = <1>; 73*4882a593Smuzhiyun device_type = "soc"; 74*4882a593Smuzhiyun compatible = "simple-bus"; 75*4882a593Smuzhiyun bus-frequency = <0>; // Filled out by uboot. 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun ecm-law@0 { 78*4882a593Smuzhiyun compatible = "fsl,ecm-law"; 79*4882a593Smuzhiyun reg = <0x0 0x1000>; 80*4882a593Smuzhiyun fsl,num-laws = <12>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun ecm@1000 { 84*4882a593Smuzhiyun compatible = "fsl,c293-ecm", "fsl,ecm"; 85*4882a593Smuzhiyun reg = <0x1000 0x1000>; 86*4882a593Smuzhiyun interrupts = <16 2 0 0>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun memory-controller@2000 { 90*4882a593Smuzhiyun compatible = "fsl,c293-memory-controller"; 91*4882a593Smuzhiyun reg = <0x2000 0x1000>; 92*4882a593Smuzhiyun interrupts = <16 2 0 0>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun/include/ "pq3-i2c-0.dtsi" 96*4882a593Smuzhiyun/include/ "pq3-i2c-1.dtsi" 97*4882a593Smuzhiyun/include/ "pq3-duart-0.dtsi" 98*4882a593Smuzhiyun/include/ "pq3-espi-0.dtsi" 99*4882a593Smuzhiyun spi0: spi@7000 { 100*4882a593Smuzhiyun fsl,espi-num-chipselects = <1>; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun/include/ "pq3-gpio-0.dtsi" 104*4882a593Smuzhiyun L2: l2-cache-controller@20000 { 105*4882a593Smuzhiyun compatible = "fsl,c293-l2-cache-controller"; 106*4882a593Smuzhiyun reg = <0x20000 0x1000>; 107*4882a593Smuzhiyun cache-line-size = <32>; // 32 bytes 108*4882a593Smuzhiyun cache-size = <0x80000>; // L2,512K 109*4882a593Smuzhiyun interrupts = <16 2 0 0>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun/include/ "pq3-dma-0.dtsi" 113*4882a593Smuzhiyun/include/ "pq3-esdhc-0.dtsi" 114*4882a593Smuzhiyun sdhc@2e000 { 115*4882a593Smuzhiyun compatible = "fsl,c293-esdhc", "fsl,esdhc"; 116*4882a593Smuzhiyun sdhci,auto-cmd12; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun crypto@80000 { 120*4882a593Smuzhiyun/include/ "qoriq-sec6.0-0.dtsi" 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun crypto@80000 { 124*4882a593Smuzhiyun reg = <0x80000 0x20000>; 125*4882a593Smuzhiyun ranges = <0x0 0x80000 0x20000>; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun jr@1000{ 128*4882a593Smuzhiyun interrupts = <45 2 0 0>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun jr@2000{ 131*4882a593Smuzhiyun interrupts = <57 2 0 0>; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun crypto@a0000 { 136*4882a593Smuzhiyun/include/ "qoriq-sec6.0-0.dtsi" 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun crypto@a0000 { 140*4882a593Smuzhiyun reg = <0xa0000 0x20000>; 141*4882a593Smuzhiyun ranges = <0x0 0xa0000 0x20000>; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun jr@1000{ 144*4882a593Smuzhiyun interrupts = <49 2 0 0>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun jr@2000{ 147*4882a593Smuzhiyun interrupts = <50 2 0 0>; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun crypto@c0000 { 152*4882a593Smuzhiyun/include/ "qoriq-sec6.0-0.dtsi" 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun crypto@c0000 { 156*4882a593Smuzhiyun reg = <0xc0000 0x20000>; 157*4882a593Smuzhiyun ranges = <0x0 0xc0000 0x20000>; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun jr@1000{ 160*4882a593Smuzhiyun interrupts = <55 2 0 0>; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun jr@2000{ 163*4882a593Smuzhiyun interrupts = <56 2 0 0>; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun/include/ "pq3-mpic.dtsi" 168*4882a593Smuzhiyun/include/ "pq3-mpic-timer-B.dtsi" 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun/include/ "pq3-etsec2-0.dtsi" 171*4882a593Smuzhiyun enet0: ethernet@b0000 { 172*4882a593Smuzhiyun queue-group@b0000 { 173*4882a593Smuzhiyun reg = <0x10000 0x1000>; 174*4882a593Smuzhiyun fsl,rx-bit-map = <0xff>; 175*4882a593Smuzhiyun fsl,tx-bit-map = <0xff>; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun/include/ "pq3-etsec2-1.dtsi" 180*4882a593Smuzhiyun enet1: ethernet@b1000 { 181*4882a593Smuzhiyun queue-group@b1000 { 182*4882a593Smuzhiyun reg = <0x11000 0x1000>; 183*4882a593Smuzhiyun fsl,rx-bit-map = <0xff>; 184*4882a593Smuzhiyun fsl,tx-bit-map = <0xff>; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun global-utilities@e0000 { 189*4882a593Smuzhiyun compatible = "fsl,c293-guts"; 190*4882a593Smuzhiyun reg = <0xe0000 0x1000>; 191*4882a593Smuzhiyun fsl,has-rstcr; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun}; 194