xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Shawn Guo <shawnguo@kernel.org>
11*4882a593Smuzhiyun
12*4882a593SmuzhiyunallOf:
13*4882a593Smuzhiyun  - $ref: "mmc-controller.yaml"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyundescription: |
16*4882a593Smuzhiyun  The Enhanced Secure Digital Host Controller on Freescale i.MX family
17*4882a593Smuzhiyun  provides an interface for MMC, SD, and SDIO types of memory cards.
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun  This file documents differences between the core properties described
20*4882a593Smuzhiyun  by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
21*4882a593Smuzhiyun
22*4882a593Smuzhiyunproperties:
23*4882a593Smuzhiyun  compatible:
24*4882a593Smuzhiyun    oneOf:
25*4882a593Smuzhiyun      - enum:
26*4882a593Smuzhiyun          - fsl,imx25-esdhc
27*4882a593Smuzhiyun          - fsl,imx35-esdhc
28*4882a593Smuzhiyun          - fsl,imx51-esdhc
29*4882a593Smuzhiyun          - fsl,imx53-esdhc
30*4882a593Smuzhiyun          - fsl,imx6q-usdhc
31*4882a593Smuzhiyun          - fsl,imx6sl-usdhc
32*4882a593Smuzhiyun          - fsl,imx6sx-usdhc
33*4882a593Smuzhiyun          - fsl,imx6ull-usdhc
34*4882a593Smuzhiyun          - fsl,imx7d-usdhc
35*4882a593Smuzhiyun          - fsl,imx7ulp-usdhc
36*4882a593Smuzhiyun      - items:
37*4882a593Smuzhiyun          - enum:
38*4882a593Smuzhiyun              - fsl,imx8mm-usdhc
39*4882a593Smuzhiyun              - fsl,imx8mn-usdhc
40*4882a593Smuzhiyun              - fsl,imx8mp-usdhc
41*4882a593Smuzhiyun              - fsl,imx8mq-usdhc
42*4882a593Smuzhiyun              - fsl,imx8qxp-usdhc
43*4882a593Smuzhiyun          - const: fsl,imx7d-usdhc
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun  reg:
46*4882a593Smuzhiyun    maxItems: 1
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun  interrupts:
49*4882a593Smuzhiyun    maxItems: 1
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun  fsl,wp-controller:
52*4882a593Smuzhiyun    description: |
53*4882a593Smuzhiyun      boolean, if present, indicate to use controller internal write protection.
54*4882a593Smuzhiyun    type: boolean
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun  fsl,delay-line:
57*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
58*4882a593Smuzhiyun    description: |
59*4882a593Smuzhiyun      Specify the number of delay cells for override mode.
60*4882a593Smuzhiyun      This is used to set the clock delay for DLL(Delay Line) on override mode
61*4882a593Smuzhiyun      to select a proper data sampling window in case the clock quality is not good
62*4882a593Smuzhiyun      due to signal path is too long on the board. Please refer to eSDHC/uSDHC
63*4882a593Smuzhiyun      chapter, DLL (Delay Line) section in RM for details.
64*4882a593Smuzhiyun    default: 0
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun  voltage-ranges:
67*4882a593Smuzhiyun    $ref: '/schemas/types.yaml#/definitions/uint32-matrix'
68*4882a593Smuzhiyun    description: |
69*4882a593Smuzhiyun      Specify the voltage range in case there are software transparent level
70*4882a593Smuzhiyun      shifters on the outputs of the controller. Two cells are required, first
71*4882a593Smuzhiyun      cell specifies minimum slot voltage (mV), second cell specifies maximum
72*4882a593Smuzhiyun      slot voltage (mV).
73*4882a593Smuzhiyun    items:
74*4882a593Smuzhiyun      items:
75*4882a593Smuzhiyun        - description: value for minimum slot voltage
76*4882a593Smuzhiyun        - description: value for maximum slot voltage
77*4882a593Smuzhiyun    maxItems: 1
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun  fsl,tuning-start-tap:
80*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
81*4882a593Smuzhiyun    description: |
82*4882a593Smuzhiyun      Specify the start delay cell point when send first CMD19 in tuning procedure.
83*4882a593Smuzhiyun    default: 0
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun  fsl,tuning-step:
86*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
87*4882a593Smuzhiyun    description: |
88*4882a593Smuzhiyun      Specify the increasing delay cell steps in tuning procedure.
89*4882a593Smuzhiyun      The uSDHC use one delay cell as default increasing step to do tuning process.
90*4882a593Smuzhiyun      This property allows user to change the tuning step to more than one delay
91*4882a593Smuzhiyun      cells which is useful for some special boards or cards when the default
92*4882a593Smuzhiyun      tuning step can't find the proper delay window within limited tuning retries.
93*4882a593Smuzhiyun    default: 0
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun  fsl,strobe-dll-delay-target:
96*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
97*4882a593Smuzhiyun    description: |
98*4882a593Smuzhiyun      Specify the strobe dll control slave delay target.
99*4882a593Smuzhiyun      This delay target programming host controller loopback read clock, and this
100*4882a593Smuzhiyun      property allows user to change the delay target for the strobe input read clock.
101*4882a593Smuzhiyun      If not use this property, driver default set the delay target to value 7.
102*4882a593Smuzhiyun      Only eMMC HS400 mode need to take care of this property.
103*4882a593Smuzhiyun    default: 0
104*4882a593Smuzhiyun
105*4882a593Smuzhiyunrequired:
106*4882a593Smuzhiyun  - compatible
107*4882a593Smuzhiyun  - reg
108*4882a593Smuzhiyun  - interrupts
109*4882a593Smuzhiyun
110*4882a593SmuzhiyununevaluatedProperties: false
111*4882a593Smuzhiyun
112*4882a593Smuzhiyunexamples:
113*4882a593Smuzhiyun  - |
114*4882a593Smuzhiyun    mmc@70004000 {
115*4882a593Smuzhiyun        compatible = "fsl,imx51-esdhc";
116*4882a593Smuzhiyun        reg = <0x70004000 0x4000>;
117*4882a593Smuzhiyun        interrupts = <1>;
118*4882a593Smuzhiyun        fsl,wp-controller;
119*4882a593Smuzhiyun    };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun    mmc@70008000 {
122*4882a593Smuzhiyun        compatible = "fsl,imx51-esdhc";
123*4882a593Smuzhiyun        reg = <0x70008000 0x4000>;
124*4882a593Smuzhiyun        interrupts = <2>;
125*4882a593Smuzhiyun        cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
126*4882a593Smuzhiyun        wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
127*4882a593Smuzhiyun    };
128