1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Freescale eSDHC controller driver generics for OF and pltfm. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2007 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * Copyright (c) 2009 MontaVista Software, Inc. 7*4882a593Smuzhiyun * Copyright (c) 2010 Pengutronix e.K. 8*4882a593Smuzhiyun * Copyright 2020 NXP 9*4882a593Smuzhiyun * Author: Wolfram Sang <kernel@pengutronix.de> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H 13*4882a593Smuzhiyun #define _DRIVERS_MMC_SDHCI_ESDHC_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Ops and quirks for the Freescale eSDHC controller. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ 20*4882a593Smuzhiyun SDHCI_QUIRK_32BIT_DMA_ADDR | \ 21*4882a593Smuzhiyun SDHCI_QUIRK_NO_BUSY_IRQ | \ 22*4882a593Smuzhiyun SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ 23*4882a593Smuzhiyun SDHCI_QUIRK_PIO_NEEDS_DELAY | \ 24*4882a593Smuzhiyun SDHCI_QUIRK_NO_HISPD_BIT) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* pltfm-specific */ 27*4882a593Smuzhiyun #define ESDHC_HOST_CONTROL_LE 0x20 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * eSDHC register definition 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Present State Register */ 34*4882a593Smuzhiyun #define ESDHC_PRSSTAT 0x24 35*4882a593Smuzhiyun #define ESDHC_CLOCK_GATE_OFF 0x00000080 36*4882a593Smuzhiyun #define ESDHC_CLOCK_STABLE 0x00000008 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Protocol Control Register */ 39*4882a593Smuzhiyun #define ESDHC_PROCTL 0x28 40*4882a593Smuzhiyun #define ESDHC_VOLT_SEL 0x00000400 41*4882a593Smuzhiyun #define ESDHC_CTRL_4BITBUS (0x1 << 1) 42*4882a593Smuzhiyun #define ESDHC_CTRL_8BITBUS (0x2 << 1) 43*4882a593Smuzhiyun #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 44*4882a593Smuzhiyun #define ESDHC_HOST_CONTROL_RES 0x01 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* System Control Register */ 47*4882a593Smuzhiyun #define ESDHC_SYSTEM_CONTROL 0x2c 48*4882a593Smuzhiyun #define ESDHC_CLOCK_MASK 0x0000fff0 49*4882a593Smuzhiyun #define ESDHC_PREDIV_SHIFT 8 50*4882a593Smuzhiyun #define ESDHC_DIVIDER_SHIFT 4 51*4882a593Smuzhiyun #define ESDHC_CLOCK_SDCLKEN 0x00000008 52*4882a593Smuzhiyun #define ESDHC_CLOCK_PEREN 0x00000004 53*4882a593Smuzhiyun #define ESDHC_CLOCK_HCKEN 0x00000002 54*4882a593Smuzhiyun #define ESDHC_CLOCK_IPGEN 0x00000001 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* System Control 2 Register */ 57*4882a593Smuzhiyun #define ESDHC_SYSTEM_CONTROL_2 0x3c 58*4882a593Smuzhiyun #define ESDHC_SMPCLKSEL 0x00800000 59*4882a593Smuzhiyun #define ESDHC_EXTN 0x00400000 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Host Controller Capabilities Register 2 */ 62*4882a593Smuzhiyun #define ESDHC_CAPABILITIES_1 0x114 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Tuning Block Control Register */ 65*4882a593Smuzhiyun #define ESDHC_TBCTL 0x120 66*4882a593Smuzhiyun #define ESDHC_HS400_WNDW_ADJUST 0x00000040 67*4882a593Smuzhiyun #define ESDHC_HS400_MODE 0x00000010 68*4882a593Smuzhiyun #define ESDHC_TB_EN 0x00000004 69*4882a593Smuzhiyun #define ESDHC_TB_MODE_MASK 0x00000003 70*4882a593Smuzhiyun #define ESDHC_TB_MODE_SW 0x00000003 71*4882a593Smuzhiyun #define ESDHC_TB_MODE_3 0x00000002 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define ESDHC_TBSTAT 0x124 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define ESDHC_TBPTR 0x128 76*4882a593Smuzhiyun #define ESDHC_WNDW_STRT_PTR_SHIFT 8 77*4882a593Smuzhiyun #define ESDHC_WNDW_STRT_PTR_MASK (0x7f << 8) 78*4882a593Smuzhiyun #define ESDHC_WNDW_END_PTR_MASK 0x7f 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* SD Clock Control Register */ 81*4882a593Smuzhiyun #define ESDHC_SDCLKCTL 0x144 82*4882a593Smuzhiyun #define ESDHC_LPBK_CLK_SEL 0x80000000 83*4882a593Smuzhiyun #define ESDHC_CMD_CLK_CTL 0x00008000 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* SD Timing Control Register */ 86*4882a593Smuzhiyun #define ESDHC_SDTIMNGCTL 0x148 87*4882a593Smuzhiyun #define ESDHC_FLW_CTL_BG 0x00008000 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* DLL Config 0 Register */ 90*4882a593Smuzhiyun #define ESDHC_DLLCFG0 0x160 91*4882a593Smuzhiyun #define ESDHC_DLL_ENABLE 0x80000000 92*4882a593Smuzhiyun #define ESDHC_DLL_RESET 0x40000000 93*4882a593Smuzhiyun #define ESDHC_DLL_FREQ_SEL 0x08000000 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* DLL Config 1 Register */ 96*4882a593Smuzhiyun #define ESDHC_DLLCFG1 0x164 97*4882a593Smuzhiyun #define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* DLL Status 0 Register */ 100*4882a593Smuzhiyun #define ESDHC_DLLSTAT0 0x170 101*4882a593Smuzhiyun #define ESDHC_DLL_STS_SLV_LOCK 0x08000000 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* Control Register for DMA transfer */ 104*4882a593Smuzhiyun #define ESDHC_DMA_SYSCTL 0x40c 105*4882a593Smuzhiyun #define ESDHC_PERIPHERAL_CLK_SEL 0x00080000 106*4882a593Smuzhiyun #define ESDHC_FLUSH_ASYNC_FIFO 0x00040000 107*4882a593Smuzhiyun #define ESDHC_DMA_SNOOP 0x00000040 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */ 110