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/OK3568_Linux_fs/u-boot/drivers/usb/dwc3/
H A Dgadget.su
H A Dcore.su
H A Ddwc3-generic.su
H A Ddwc3-generic.c3 * Generic DWC3 Glue layer
7 * Based on dwc3-omap.c.
15 #include <dwc3-uboot.h>
40 struct dwc3 dwc3; member
55 struct dwc3 *dwc3 = &priv->dwc3; in dwc3_generic_probe() local
58 dwc3->dev = dev; in dwc3_generic_probe()
59 dwc3->maximum_speed = plat->maximum_speed; in dwc3_generic_probe()
60 dwc3->dr_mode = plat->dr_mode; in dwc3_generic_probe()
62 dwc3_of_parse(dwc3); in dwc3_generic_probe()
69 if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) { in dwc3_generic_probe()
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H A Dep0.su
H A Dcore.c9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
12 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
20 #include <dwc3-uboot.h>
39 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) in dwc3_set_mode()
53 static int dwc3_core_soft_reset(struct dwc3 *dwc) in dwc3_core_soft_reset()
99 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, in dwc3_free_one_event_buffer()
113 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, in dwc3_alloc_one_event_buffer()
139 static void dwc3_free_event_buffers(struct dwc3 *dwc) in dwc3_free_event_buffers()
159 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) in dwc3_alloc_event_buffers()
192 static int dwc3_event_buffers_setup(struct dwc3 *dwc) in dwc3_event_buffers_setup()
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H A D.built-in.o.cmd
/OK3568_Linux_fs/kernel/drivers/usb/dwc3/
H A DMakefile5 obj-$(CONFIG_USB_DWC3) += dwc3.o
7 dwc3-y := core.o
10 dwc3-y += trace.o
14 dwc3-y += host.o
18 dwc3-y += gadget.o ep0.o
22 dwc3-y += drd.o
26 dwc3-y += ulpi.o
30 dwc3-y += debugfs.o
45 obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
46 obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o
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H A Ddwc3-imx8mp.c3 * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
41 struct platform_device *dwc3; member
52 struct dwc3 *dwc3 = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_wakeup_enable() local
55 if (!dwc3) in dwc3_imx8mp_wakeup_enable()
60 if ((dwc3->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc3->xhci) in dwc3_imx8mp_wakeup_enable()
63 else if (dwc3->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) in dwc3_imx8mp_wakeup_enable()
82 struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_interrupt()
168 dwc3_np = of_get_child_by_name(node, "dwc3"); in dwc3_imx8mp_probe()
171 dev_err(dev, "failed to find dwc3 core child\n"); in dwc3_imx8mp_probe()
177 dev_err(&pdev->dev, "failed to create dwc3 core\n"); in dwc3_imx8mp_probe()
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H A Ddwc3-haps.c3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer
20 * @dwc3: child dwc3 platform_device
24 struct platform_device *dwc3; member
56 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
57 if (!dwc->dwc3) in dwc3_haps_probe()
71 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
73 dev_err(dev, "couldn't add resources to dwc3 device\n"); in dwc3_haps_probe()
78 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
80 ret = platform_device_add_properties(dwc->dwc3, initial_properties); in dwc3_haps_probe()
84 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
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H A Ddwc3-pci.c3 * dwc3-pci.c - PCI Specific glue layer
58 * @dwc3: child dwc3 platform_device
65 struct platform_device *dwc3; member
226 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work() local
229 ret = pm_runtime_get_sync(&dwc3->dev); in dwc3_pci_resume_work()
231 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
235 pm_runtime_mark_last_busy(&dwc3->dev); in dwc3_pci_resume_work()
236 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
259 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_pci_probe()
260 if (!dwc->dwc3) in dwc3_pci_probe()
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H A Dcore.c47 static int dwc3_get_dr_mode(struct dwc3 *dwc) in dwc3_get_dr_mode()
90 !DWC3_VER_IS_PRIOR(DWC3, 330A)) in dwc3_get_dr_mode()
105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) in dwc3_set_prtcap()
119 struct dwc3 *dwc = work_to_dwc(work); in __dwc3_set_mode()
176 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || in __dwc3_set_mode()
266 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) in dwc3_set_mode()
282 struct dwc3 *dwc = dep->dwc; in dwc3_core_fifo_space()
298 int dwc3_core_soft_reset(struct dwc3 *dwc) in dwc3_core_soft_reset()
305 * XHCI driver will reset the host block. If dwc3 was configured for in dwc3_core_soft_reset()
336 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); in dwc3_core_soft_reset()
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H A Ddwc3-qcom.c4 * Inspired by dwc3-of-simple.c
69 struct platform_device *dwc3; member
264 if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER || in dwc3_qcom_interconnect_init()
265 usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN) in dwc3_qcom_interconnect_init()
302 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_is_host()
416 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in qcom_dwc3_resume_irq()
434 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ in dwc3_qcom_select_utmi_clk()
598 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_qcom_acpi_register_core()
599 if (!qcom->dwc3) in dwc3_qcom_acpi_register_core()
602 qcom->dwc3->dev.parent = dev; in dwc3_qcom_acpi_register_core()
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H A Dgadget.c41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) in dwc3_gadget_set_test_mode()
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc) in dwc3_gadget_get_link_state()
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) in dwc3_gadget_set_link_state()
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) { in dwc3_gadget_set_link_state()
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) in dwc3_gadget_set_link_state()
178 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_del_and_unmap_request()
211 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_giveback()
230 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, in dwc3_send_gadget_generic_command()
261 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
276 struct dwc3 *dwc = dep->dwc; in dwc3_send_gadget_ep_cmd()
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H A Dcore.h78 /* DWC3 registers memory space boundries */
668 struct dwc3 *dwc;
718 struct dwc3 *dwc;
913 * @status: internal dwc3 request status tracking
966 * struct dwc3 - representation of our controller
1056 * @has_hibernation: true when dwc3 was configured with Hibernation
1057 * @sysdev_is_parent: true when dwc3 device has a parent driver
1065 * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
1114 struct dwc3 { struct
1335 * struct dwc3_vendor - contains parameters without modifying the format of DWC3 core
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H A Dep0.c30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
38 struct dwc3 *dwc; in dwc3_ep0_prepare_one_trb()
66 struct dwc3 *dwc; in dwc3_ep0_start_trans()
90 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_queue()
193 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_queue()
221 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) in dwc3_ep0_stall_and_restart()
251 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_set_halt()
261 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_set_halt()
272 void dwc3_ep0_out_start(struct dwc3 *dwc) in dwc3_ep0_out_start()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/
H A Dqcom,dwc3.yaml4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
16 - qcom,msm8996-dwc3
17 - qcom,msm8998-dwc3
18 - qcom,sc7180-dwc3
19 - qcom,sdm845-dwc3
20 - qcom,sdx55-dwc3
21 - qcom,sm8150-dwc3
22 - qcom,sm8250-dwc3
23 - qcom,sm8350-dwc3
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H A Ddwc3-st.txt1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
33 example below. The DT binding details of dwc3 can be found in:
34 Documentation/devicetree/bindings/usb/dwc3.txt
37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
44 st_dwc3: dwc3@8f94000 {
45 compatible = "st,stih407-dwc3";
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H A Drockchip,dwc3.txt1 Rockchip SuperSpeed DWC3 USB SoC controller
4 - compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
15 A child node must exist to represent the core DWC3 IP block. The name of
16 the node is not important. The content of the node is defined in dwc3.txt.
25 compatible = "rockchip,rk3399-dwc3";
33 usbdrd_dwc3_0: dwc3@fe800000 {
34 compatible = "snps,dwc3";
42 compatible = "rockchip,rk3399-dwc3";
50 usbdrd_dwc3_1: dwc3@fe900000 {
51 compatible = "snps,dwc3";
H A Dintel,keembay-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/intel,keembay-dwc3.yaml#
7 title: Intel Keem Bay DWC3 USB controller
14 const: intel,keembay-dwc3
37 "^dwc3@[0-9a-f]+$":
40 A child node must exist to represent the core DWC3 IP block.
41 The content of the node is defined in dwc3.txt.
61 compatible = "intel,keembay-dwc3";
71 dwc3@34000000 {
72 compatible = "snps,dwc3";
H A Domap-usb.txt46 OMAP DWC3 GLUE
48 * "ti,dwc3" for OMAP5 and DRA7
49 * "ti,am437x-dwc3" for AM437x
60 - extcon : phandle for the extcon device omap dwc3 uses to detect
65 The dwc3 core should be added as subnode to omap dwc3 glue.
66 - dwc3 :
67 The binding details of dwc3 can be found in:
68 Documentation/devicetree/bindings/usb/dwc3.txt
71 compatible = "ti,dwc3";
H A Dexynos-usb.txt68 DWC3
71 "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
73 "samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on
75 "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
93 The dwc3 core should be added as subnode to Exynos dwc3 glue.
94 - dwc3 :
95 The binding details of dwc3 can be found in:
96 Documentation/devicetree/bindings/usb/dwc3.txt
109 dwc3 {
110 compatible = "synopsys,dwc3";
H A Dfsl,imx8mp-dwc3.yaml5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
15 const: fsl,imx8mp-dwc3
20 dwc3 core on the SOC.
55 "^dwc3@[0-9a-f]+$":
58 A child node must exist to represent the core DWC3 IP block
59 The content of the node is defined in dwc3.txt.
79 compatible = "fsl,imx8mp-dwc3";
90 dwc3@38100000 {
91 compatible = "snps,dwc3";
/OK3568_Linux_fs/u-boot/drivers/usb/host/
H A Ddwc3-sti-glue.c2 * STiH407 family DWC3 specific Glue layer
20 #include <linux/usb/dwc3.h>
22 #include <dwc3-sti-glue.h>
27 * struct sti_dwc3_glue_platdata - dwc3 STi glue driver private structure
113 pr_err("unable to find st,stih407-dwc3 reg property(%d)\n", ret); in sti_dwc3_glue_ofdata_to_platdata()
156 /* Find snps,dwc3 node from subnode */ in sti_dwc3_glue_bind()
158 if (ofnode_device_is_compatible(node, "snps,dwc3")) in sti_dwc3_glue_bind()
163 pr_err("Can't find dwc3 subnode for %s\n", dev->name); in sti_dwc3_glue_bind()
167 /* retrieve the DWC3 dual role mode */ in sti_dwc3_glue_bind()
184 pr_err("DWC3 powerdown reset deassert failed: %d", ret); in sti_dwc3_glue_probe()
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H A Dxhci-dwc3.c4 * DWC3 controller driver
15 #include <dwc3-uboot.h>
19 #include <linux/usb/dwc3.h>
29 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) in dwc3_set_mode()
36 static void dwc3_phy_reset(struct dwc3 *dwc3_reg) in dwc3_phy_reset()
53 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) in dwc3_core_soft_reset()
67 int dwc3_core_init(struct dwc3 *dwc3_reg) in dwc3_core_init()
96 * WORKAROUND: DWC3 revisions <1.90a have a bug in dwc3_core_init()
109 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) in dwc3_set_fladj()
120 struct dwc3 *dwc3_reg; in xhci_dwc3_probe()
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