1 /*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * DWC3 controller driver
5 *
6 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <common.h>
12 #include <dm.h>
13 #include <generic-phy.h>
14 #include <usb.h>
15 #include <dwc3-uboot.h>
16
17 #include <usb/xhci.h>
18 #include <asm/io.h>
19 #include <linux/usb/dwc3.h>
20 #include <linux/usb/otg.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 struct xhci_dwc3_platdata {
25 struct phy *usb_phys;
26 int num_phys;
27 };
28
dwc3_set_mode(struct dwc3 * dwc3_reg,u32 mode)29 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
30 {
31 clrsetbits_le32(&dwc3_reg->g_ctl,
32 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
33 DWC3_GCTL_PRTCAPDIR(mode));
34 }
35
dwc3_phy_reset(struct dwc3 * dwc3_reg)36 static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
37 {
38 /* Assert USB3 PHY reset */
39 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
40
41 /* Assert USB2 PHY reset */
42 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
43
44 mdelay(100);
45
46 /* Clear USB3 PHY reset */
47 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
48
49 /* Clear USB2 PHY reset */
50 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
51 }
52
dwc3_core_soft_reset(struct dwc3 * dwc3_reg)53 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
54 {
55 /* Before Resetting PHY, put Core in Reset */
56 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
57
58 /* reset USB3 phy - if required */
59 dwc3_phy_reset(dwc3_reg);
60
61 mdelay(100);
62
63 /* After PHYs are stable we can take Core out of reset state */
64 clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
65 }
66
dwc3_core_init(struct dwc3 * dwc3_reg)67 int dwc3_core_init(struct dwc3 *dwc3_reg)
68 {
69 u32 reg;
70 u32 revision;
71 unsigned int dwc3_hwparams1;
72
73 revision = readl(&dwc3_reg->g_snpsid);
74 /* This should read as U3 followed by revision number */
75 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
76 puts("this is not a DesignWare USB3 DRD Core\n");
77 return -1;
78 }
79
80 dwc3_core_soft_reset(dwc3_reg);
81
82 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
83
84 reg = readl(&dwc3_reg->g_ctl);
85 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
86 reg &= ~DWC3_GCTL_DISSCRAMBLE;
87 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
88 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
89 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
90 break;
91 default:
92 debug("No power optimization available\n");
93 }
94
95 /*
96 * WORKAROUND: DWC3 revisions <1.90a have a bug
97 * where the device can fail to connect at SuperSpeed
98 * and falls back to high-speed mode which causes
99 * the device to enter a Connect/Disconnect loop
100 */
101 if ((revision & DWC3_REVISION_MASK) < 0x190a)
102 reg |= DWC3_GCTL_U2RSTECN;
103
104 writel(reg, &dwc3_reg->g_ctl);
105
106 return 0;
107 }
108
dwc3_set_fladj(struct dwc3 * dwc3_reg,u32 val)109 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
110 {
111 setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
112 GFLADJ_30MHZ(val));
113 }
114
115 #if CONFIG_IS_ENABLED(DM_USB)
xhci_dwc3_probe(struct udevice * dev)116 static int xhci_dwc3_probe(struct udevice *dev)
117 {
118 struct xhci_hcor *hcor;
119 struct xhci_hccr *hccr;
120 struct dwc3 *dwc3_reg;
121 enum usb_dr_mode dr_mode;
122 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
123 const char *phy;
124 u32 reg;
125 int ret;
126
127 hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
128 hcor = (struct xhci_hcor *)((uintptr_t)hccr +
129 HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
130
131 ret = dwc3_setup_phy(dev, &plat->usb_phys, &plat->num_phys);
132 if (ret && (ret != -ENOTSUPP))
133 return ret;
134
135 dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
136
137 dwc3_core_init(dwc3_reg);
138
139 /* Set dwc3 usb2 phy config */
140 reg = readl(&dwc3_reg->g_usb2phycfg[0]);
141
142 phy = dev_read_string(dev, "phy_type");
143 if (phy && strcmp(phy, "utmi_wide") == 0) {
144 reg |= DWC3_GUSB2PHYCFG_PHYIF;
145 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
146 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
147 }
148
149 if (dev_read_bool(dev, "snps,dis_enblslpm-quirk"))
150 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
151
152 if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
153 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
154
155 if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
156 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
157
158 writel(reg, &dwc3_reg->g_usb2phycfg[0]);
159
160 dr_mode = usb_get_dr_mode(dev->node);
161 if (dr_mode == USB_DR_MODE_UNKNOWN)
162 /* by default set dual role mode to HOST */
163 dr_mode = USB_DR_MODE_HOST;
164
165 dwc3_set_mode(dwc3_reg, dr_mode);
166
167 return xhci_register(dev, hccr, hcor);
168 }
169
xhci_dwc3_remove(struct udevice * dev)170 static int xhci_dwc3_remove(struct udevice *dev)
171 {
172 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
173
174 dwc3_shutdown_phy(dev, plat->usb_phys, plat->num_phys);
175
176 return xhci_deregister(dev);
177 }
178
179 static const struct udevice_id xhci_dwc3_ids[] = {
180 { .compatible = "snps,dwc3" },
181 { }
182 };
183
184 U_BOOT_DRIVER(xhci_dwc3) = {
185 .name = "xhci-dwc3",
186 .id = UCLASS_USB,
187 .of_match = xhci_dwc3_ids,
188 .probe = xhci_dwc3_probe,
189 .remove = xhci_dwc3_remove,
190 .ops = &xhci_usb_ops,
191 .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
192 .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
193 .flags = DM_FLAG_ALLOC_PRIV_DMA,
194 };
195 #endif
196