1*4882a593SmuzhiyunRockchip SuperSpeed DWC3 USB SoC controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC 5*4882a593Smuzhiyun- clocks: A list of phandle + clock-specifier pairs for the 6*4882a593Smuzhiyun clocks listed in clock-names 7*4882a593Smuzhiyun- clock-names: Should contain the following: 8*4882a593Smuzhiyun "ref_clk" Controller reference clk, have to be 24 MHz 9*4882a593Smuzhiyun "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz 10*4882a593Smuzhiyun "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS 11*4882a593Smuzhiyun operation and >= 30MHz for HS operation 12*4882a593Smuzhiyun "grf_clk" Controller grf clk 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRequired child node: 15*4882a593SmuzhiyunA child node must exist to represent the core DWC3 IP block. The name of 16*4882a593Smuzhiyunthe node is not important. The content of the node is defined in dwc3.txt. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunPhy documentation is provided in the following places: 19*4882a593SmuzhiyunDocumentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY 20*4882a593SmuzhiyunDocumentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample device nodes: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun usbdrd3_0: usb@fe800000 { 25*4882a593Smuzhiyun compatible = "rockchip,rk3399-dwc3"; 26*4882a593Smuzhiyun clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 27*4882a593Smuzhiyun <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; 28*4882a593Smuzhiyun clock-names = "ref_clk", "suspend_clk", 29*4882a593Smuzhiyun "bus_clk", "grf_clk"; 30*4882a593Smuzhiyun #address-cells = <2>; 31*4882a593Smuzhiyun #size-cells = <2>; 32*4882a593Smuzhiyun ranges; 33*4882a593Smuzhiyun usbdrd_dwc3_0: dwc3@fe800000 { 34*4882a593Smuzhiyun compatible = "snps,dwc3"; 35*4882a593Smuzhiyun reg = <0x0 0xfe800000 0x0 0x100000>; 36*4882a593Smuzhiyun interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 37*4882a593Smuzhiyun dr_mode = "otg"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun usbdrd3_1: usb@fe900000 { 42*4882a593Smuzhiyun compatible = "rockchip,rk3399-dwc3"; 43*4882a593Smuzhiyun clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 44*4882a593Smuzhiyun <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; 45*4882a593Smuzhiyun clock-names = "ref_clk", "suspend_clk", 46*4882a593Smuzhiyun "bus_clk", "grf_clk"; 47*4882a593Smuzhiyun #address-cells = <2>; 48*4882a593Smuzhiyun #size-cells = <2>; 49*4882a593Smuzhiyun ranges; 50*4882a593Smuzhiyun usbdrd_dwc3_1: dwc3@fe900000 { 51*4882a593Smuzhiyun compatible = "snps,dwc3"; 52*4882a593Smuzhiyun reg = <0x0 0xfe900000 0x0 0x100000>; 53*4882a593Smuzhiyun interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 54*4882a593Smuzhiyun dr_mode = "otg"; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57