1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/usb/intel,keembay-dwc3.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Intel Keem Bay DWC3 USB controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun const: intel,keembay-dwc3 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun clocks: 17*4882a593Smuzhiyun maxItems: 4 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun clock-names: 20*4882a593Smuzhiyun items: 21*4882a593Smuzhiyun - const: async_master 22*4882a593Smuzhiyun - const: ref 23*4882a593Smuzhiyun - const: alt_ref 24*4882a593Smuzhiyun - const: suspend 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun ranges: true 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun '#address-cells': 29*4882a593Smuzhiyun enum: [ 1, 2 ] 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun '#size-cells': 32*4882a593Smuzhiyun enum: [ 1, 2 ] 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun# Required child node: 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunpatternProperties: 37*4882a593Smuzhiyun "^dwc3@[0-9a-f]+$": 38*4882a593Smuzhiyun type: object 39*4882a593Smuzhiyun description: 40*4882a593Smuzhiyun A child node must exist to represent the core DWC3 IP block. 41*4882a593Smuzhiyun The content of the node is defined in dwc3.txt. 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunrequired: 44*4882a593Smuzhiyun - compatible 45*4882a593Smuzhiyun - clocks 46*4882a593Smuzhiyun - clock-names 47*4882a593Smuzhiyun - ranges 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunadditionalProperties: false 50*4882a593Smuzhiyun 51*4882a593Smuzhiyunexamples: 52*4882a593Smuzhiyun - | 53*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 54*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/irq.h> 55*4882a593Smuzhiyun #define KEEM_BAY_A53_AUX_USB 56*4882a593Smuzhiyun #define KEEM_BAY_A53_AUX_USB_REF 57*4882a593Smuzhiyun #define KEEM_BAY_A53_AUX_USB_ALT_REF 58*4882a593Smuzhiyun #define KEEM_BAY_A53_AUX_USB_SUSPEND 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun usb { 61*4882a593Smuzhiyun compatible = "intel,keembay-dwc3"; 62*4882a593Smuzhiyun clocks = <&scmi_clk KEEM_BAY_A53_AUX_USB>, 63*4882a593Smuzhiyun <&scmi_clk KEEM_BAY_A53_AUX_USB_REF>, 64*4882a593Smuzhiyun <&scmi_clk KEEM_BAY_A53_AUX_USB_ALT_REF>, 65*4882a593Smuzhiyun <&scmi_clk KEEM_BAY_A53_AUX_USB_SUSPEND>; 66*4882a593Smuzhiyun clock-names = "async_master", "ref", "alt_ref", "suspend"; 67*4882a593Smuzhiyun ranges; 68*4882a593Smuzhiyun #address-cells = <1>; 69*4882a593Smuzhiyun #size-cells = <1>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun dwc3@34000000 { 72*4882a593Smuzhiyun compatible = "snps,dwc3"; 73*4882a593Smuzhiyun reg = <0x34000000 0x10000>; 74*4882a593Smuzhiyun interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 75*4882a593Smuzhiyun dr_mode = "peripheral"; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78