1 // SPDX-License-Identifier: GPL-2.0
2 /**
3 * dwc3-pci.c - PCI Specific glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/slab.h>
14 #include <linux/pci.h>
15 #include <linux/workqueue.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/platform_device.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/gpio/machine.h>
20 #include <linux/acpi.h>
21 #include <linux/delay.h>
22
23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
39 #define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e
40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
41 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
42 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee
43 #define PCI_DEVICE_ID_INTEL_ADLP 0x51ee
44 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1
45 #define PCI_DEVICE_ID_INTEL_TGL 0x9a15
46
47 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
48 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
49 #define PCI_INTEL_BXT_STATE_D0 0
50 #define PCI_INTEL_BXT_STATE_D3 3
51
52 #define GP_RWBAR 1
53 #define GP_RWREG1 0xa0
54 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
55
56 /**
57 * struct dwc3_pci - Driver private structure
58 * @dwc3: child dwc3 platform_device
59 * @pci: our link to PCI bus
60 * @guid: _DSM GUID
61 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
62 * @wakeup_work: work for asynchronous resume
63 */
64 struct dwc3_pci {
65 struct platform_device *dwc3;
66 struct pci_dev *pci;
67
68 guid_t guid;
69
70 unsigned int has_dsm_for_pm:1;
71 struct work_struct wakeup_work;
72 };
73
74 static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
75 static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
76
77 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
78 { "reset-gpios", &reset_gpios, 1 },
79 { "cs-gpios", &cs_gpios, 1 },
80 { },
81 };
82
83 static struct gpiod_lookup_table platform_bytcr_gpios = {
84 .dev_id = "0000:00:16.0",
85 .table = {
86 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
87 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
88 {}
89 },
90 };
91
dwc3_byt_enable_ulpi_refclock(struct pci_dev * pci)92 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
93 {
94 void __iomem *reg;
95 u32 value;
96
97 reg = pcim_iomap(pci, GP_RWBAR, 0);
98 if (!reg)
99 return -ENOMEM;
100
101 value = readl(reg + GP_RWREG1);
102 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
103 goto unmap; /* ULPI refclk already enabled */
104
105 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
106 writel(value, reg + GP_RWREG1);
107 /* This comes from the Intel Android x86 tree w/o any explanation */
108 msleep(100);
109 unmap:
110 pcim_iounmap(pci, reg);
111 return 0;
112 }
113
114 static const struct property_entry dwc3_pci_intel_properties[] = {
115 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
116 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
117 {}
118 };
119
120 static const struct property_entry dwc3_pci_mrfld_properties[] = {
121 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
122 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
123 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
124 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
125 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
126 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
127 {}
128 };
129
130 static const struct property_entry dwc3_pci_amd_properties[] = {
131 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
132 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
133 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
134 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
135 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
136 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
137 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
138 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
139 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
140 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
141 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
142 /* FIXME these quirks should be removed when AMD NL tapes out */
143 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
144 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
145 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
146 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
147 {}
148 };
149
150 static const struct software_node dwc3_pci_intel_swnode = {
151 .properties = dwc3_pci_intel_properties,
152 };
153
154 static const struct software_node dwc3_pci_intel_mrfld_swnode = {
155 .properties = dwc3_pci_mrfld_properties,
156 };
157
158 static const struct software_node dwc3_pci_amd_swnode = {
159 .properties = dwc3_pci_amd_properties,
160 };
161
dwc3_pci_quirks(struct dwc3_pci * dwc)162 static int dwc3_pci_quirks(struct dwc3_pci *dwc)
163 {
164 struct pci_dev *pdev = dwc->pci;
165
166 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
167 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
168 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
169 pdev->device == PCI_DEVICE_ID_INTEL_EHLLP) {
170 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
171 dwc->has_dsm_for_pm = true;
172 }
173
174 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
175 struct gpio_desc *gpio;
176 int ret;
177
178 /* On BYT the FW does not always enable the refclock */
179 ret = dwc3_byt_enable_ulpi_refclock(pdev);
180 if (ret)
181 return ret;
182
183 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
184 acpi_dwc3_byt_gpios);
185 if (ret)
186 dev_dbg(&pdev->dev, "failed to add mapping table\n");
187
188 /*
189 * A lot of BYT devices lack ACPI resource entries for
190 * the GPIOs, add a fallback mapping to the reference
191 * design GPIOs which all boards seem to use.
192 */
193 gpiod_add_lookup_table(&platform_bytcr_gpios);
194
195 /*
196 * These GPIOs will turn on the USB2 PHY. Note that we have to
197 * put the gpio descriptors again here because the phy driver
198 * might want to grab them, too.
199 */
200 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
201 if (IS_ERR(gpio))
202 return PTR_ERR(gpio);
203
204 gpiod_set_value_cansleep(gpio, 1);
205 gpiod_put(gpio);
206
207 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
208 if (IS_ERR(gpio))
209 return PTR_ERR(gpio);
210
211 if (gpio) {
212 gpiod_set_value_cansleep(gpio, 1);
213 gpiod_put(gpio);
214 usleep_range(10000, 11000);
215 }
216 }
217 }
218
219 return 0;
220 }
221
222 #ifdef CONFIG_PM
dwc3_pci_resume_work(struct work_struct * work)223 static void dwc3_pci_resume_work(struct work_struct *work)
224 {
225 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
226 struct platform_device *dwc3 = dwc->dwc3;
227 int ret;
228
229 ret = pm_runtime_get_sync(&dwc3->dev);
230 if (ret < 0) {
231 pm_runtime_put_sync_autosuspend(&dwc3->dev);
232 return;
233 }
234
235 pm_runtime_mark_last_busy(&dwc3->dev);
236 pm_runtime_put_sync_autosuspend(&dwc3->dev);
237 }
238 #endif
239
dwc3_pci_probe(struct pci_dev * pci,const struct pci_device_id * id)240 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
241 {
242 struct dwc3_pci *dwc;
243 struct resource res[2];
244 int ret;
245 struct device *dev = &pci->dev;
246
247 ret = pcim_enable_device(pci);
248 if (ret) {
249 dev_err(dev, "failed to enable pci device\n");
250 return -ENODEV;
251 }
252
253 pci_set_master(pci);
254
255 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
256 if (!dwc)
257 return -ENOMEM;
258
259 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
260 if (!dwc->dwc3)
261 return -ENOMEM;
262
263 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
264
265 res[0].start = pci_resource_start(pci, 0);
266 res[0].end = pci_resource_end(pci, 0);
267 res[0].name = "dwc_usb3";
268 res[0].flags = IORESOURCE_MEM;
269
270 res[1].start = pci->irq;
271 res[1].name = "dwc_usb3";
272 res[1].flags = IORESOURCE_IRQ;
273
274 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
275 if (ret) {
276 dev_err(dev, "couldn't add resources to dwc3 device\n");
277 goto err;
278 }
279
280 dwc->pci = pci;
281 dwc->dwc3->dev.parent = dev;
282 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
283
284 ret = device_add_software_node(&dwc->dwc3->dev, (void *)id->driver_data);
285 if (ret < 0)
286 goto err;
287
288 ret = dwc3_pci_quirks(dwc);
289 if (ret)
290 goto err;
291
292 ret = platform_device_add(dwc->dwc3);
293 if (ret) {
294 dev_err(dev, "failed to register dwc3 device\n");
295 goto err;
296 }
297
298 device_init_wakeup(dev, true);
299 pci_set_drvdata(pci, dwc);
300 pm_runtime_put(dev);
301 #ifdef CONFIG_PM
302 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
303 #endif
304
305 return 0;
306 err:
307 device_remove_software_node(&dwc->dwc3->dev);
308 platform_device_put(dwc->dwc3);
309 return ret;
310 }
311
dwc3_pci_remove(struct pci_dev * pci)312 static void dwc3_pci_remove(struct pci_dev *pci)
313 {
314 struct dwc3_pci *dwc = pci_get_drvdata(pci);
315 struct pci_dev *pdev = dwc->pci;
316
317 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
318 gpiod_remove_lookup_table(&platform_bytcr_gpios);
319 #ifdef CONFIG_PM
320 cancel_work_sync(&dwc->wakeup_work);
321 #endif
322 device_init_wakeup(&pci->dev, false);
323 pm_runtime_get(&pci->dev);
324 device_remove_software_node(&dwc->dwc3->dev);
325 platform_device_unregister(dwc->dwc3);
326 }
327
328 static const struct pci_device_id dwc3_pci_id_table[] = {
329 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
330 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
331
332 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
333 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
334
335 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
336 (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, },
337
338 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
339 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
340
341 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
342 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
343
344 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
345 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
346
347 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
348 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
349
350 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
351 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
352
353 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
354 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
355
356 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
357 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
358
359 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
360 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
361
362 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
363 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
364
365 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
366 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
367
368 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
369 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
370
371 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
372 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
373
374 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
375 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
376
377 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP),
378 (kernel_ulong_t) &dwc3_pci_intel_swnode },
379
380 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
381 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
382
383 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
384 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
385
386 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
387 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
388
389 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP),
390 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
391
392 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS),
393 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
394
395 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL),
396 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
397
398 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
399 (kernel_ulong_t) &dwc3_pci_amd_swnode, },
400 { } /* Terminating Entry */
401 };
402 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
403
404 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
dwc3_pci_dsm(struct dwc3_pci * dwc,int param)405 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
406 {
407 union acpi_object *obj;
408 union acpi_object tmp;
409 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
410
411 if (!dwc->has_dsm_for_pm)
412 return 0;
413
414 tmp.type = ACPI_TYPE_INTEGER;
415 tmp.integer.value = param;
416
417 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
418 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
419 if (!obj) {
420 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
421 return -EIO;
422 }
423
424 ACPI_FREE(obj);
425
426 return 0;
427 }
428 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
429
430 #ifdef CONFIG_PM
dwc3_pci_runtime_suspend(struct device * dev)431 static int dwc3_pci_runtime_suspend(struct device *dev)
432 {
433 struct dwc3_pci *dwc = dev_get_drvdata(dev);
434
435 if (device_can_wakeup(dev))
436 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
437
438 return -EBUSY;
439 }
440
dwc3_pci_runtime_resume(struct device * dev)441 static int dwc3_pci_runtime_resume(struct device *dev)
442 {
443 struct dwc3_pci *dwc = dev_get_drvdata(dev);
444 int ret;
445
446 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
447 if (ret)
448 return ret;
449
450 queue_work(pm_wq, &dwc->wakeup_work);
451
452 return 0;
453 }
454 #endif /* CONFIG_PM */
455
456 #ifdef CONFIG_PM_SLEEP
dwc3_pci_suspend(struct device * dev)457 static int dwc3_pci_suspend(struct device *dev)
458 {
459 struct dwc3_pci *dwc = dev_get_drvdata(dev);
460
461 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
462 }
463
dwc3_pci_resume(struct device * dev)464 static int dwc3_pci_resume(struct device *dev)
465 {
466 struct dwc3_pci *dwc = dev_get_drvdata(dev);
467
468 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
469 }
470 #endif /* CONFIG_PM_SLEEP */
471
472 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
473 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
474 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
475 NULL)
476 };
477
478 static struct pci_driver dwc3_pci_driver = {
479 .name = "dwc3-pci",
480 .id_table = dwc3_pci_id_table,
481 .probe = dwc3_pci_probe,
482 .remove = dwc3_pci_remove,
483 .driver = {
484 .pm = &dwc3_pci_dev_pm_ops,
485 }
486 };
487
488 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
489 MODULE_LICENSE("GPL v2");
490 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
491
492 module_pci_driver(dwc3_pci_driver);
493