1*4882a593SmuzhiyunSamsung Exynos SoC USB controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe USB devices interface with USB controllers on Exynos SOCs. 4*4882a593SmuzhiyunThe device node has following properties. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunEHCI 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun - compatible: should be "samsung,exynos4210-ehci" for USB 2.0 9*4882a593Smuzhiyun EHCI controller in host mode. 10*4882a593Smuzhiyun - reg: physical base address of the controller and length of memory mapped 11*4882a593Smuzhiyun region. 12*4882a593Smuzhiyun - interrupts: interrupt number to the cpu. 13*4882a593Smuzhiyun - clocks: from common clock binding: handle to usb clock. 14*4882a593Smuzhiyun - clock-names: from common clock binding: Shall be "usbhost". 15*4882a593Smuzhiyun - phys: from the *Generic PHY* bindings; array specifying phy(s) used 16*4882a593Smuzhiyun by the root port. 17*4882a593Smuzhiyun - phy-names: from the *Generic PHY* bindings; array of the names for 18*4882a593Smuzhiyun each phy for the root ports, must be a subset of the following: 19*4882a593Smuzhiyun "host", "hsic0", "hsic1". 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunOptional properties: 22*4882a593Smuzhiyun - samsung,vbus-gpio: if present, specifies the GPIO that 23*4882a593Smuzhiyun needs to be pulled up for the bus to be powered. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun usb@12110000 { 28*4882a593Smuzhiyun compatible = "samsung,exynos4210-ehci"; 29*4882a593Smuzhiyun reg = <0x12110000 0x100>; 30*4882a593Smuzhiyun interrupts = <0 71 0>; 31*4882a593Smuzhiyun samsung,vbus-gpio = <&gpx2 6 1 3 3>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clocks = <&clock 285>; 34*4882a593Smuzhiyun clock-names = "usbhost"; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun phys = <&usb2phy 1>; 37*4882a593Smuzhiyun phy-names = "host"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunOHCI 41*4882a593SmuzhiyunRequired properties: 42*4882a593Smuzhiyun - compatible: should be "samsung,exynos4210-ohci" for USB 2.0 43*4882a593Smuzhiyun OHCI companion controller in host mode. 44*4882a593Smuzhiyun - reg: physical base address of the controller and length of memory mapped 45*4882a593Smuzhiyun region. 46*4882a593Smuzhiyun - interrupts: interrupt number to the cpu. 47*4882a593Smuzhiyun - clocks: from common clock binding: handle to usb clock. 48*4882a593Smuzhiyun - clock-names: from common clock binding: Shall be "usbhost". 49*4882a593Smuzhiyun - phys: from the *Generic PHY* bindings; array specifying phy(s) used 50*4882a593Smuzhiyun by the root port. 51*4882a593Smuzhiyun - phy-names: from the *Generic PHY* bindings; array of the names for 52*4882a593Smuzhiyun each phy for the root ports, must be a subset of the following: 53*4882a593Smuzhiyun "host", "hsic0", "hsic1". 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunExample: 56*4882a593Smuzhiyun usb@12120000 { 57*4882a593Smuzhiyun compatible = "samsung,exynos4210-ohci"; 58*4882a593Smuzhiyun reg = <0x12120000 0x100>; 59*4882a593Smuzhiyun interrupts = <0 71 0>; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun clocks = <&clock 285>; 62*4882a593Smuzhiyun clock-names = "usbhost"; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun phys = <&usb2phy 1>; 65*4882a593Smuzhiyun phy-names = "host"; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593SmuzhiyunDWC3 69*4882a593SmuzhiyunRequired properties: 70*4882a593Smuzhiyun - compatible: should be one of the following - 71*4882a593Smuzhiyun "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on 72*4882a593Smuzhiyun Exynos5250/5420. 73*4882a593Smuzhiyun "samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on 74*4882a593Smuzhiyun Exynos5433. 75*4882a593Smuzhiyun "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7. 76*4882a593Smuzhiyun - #address-cells, #size-cells : should be '1' if the device has sub-nodes 77*4882a593Smuzhiyun with 'reg' property. 78*4882a593Smuzhiyun - ranges: allows valid 1:1 translation between child's address space and 79*4882a593Smuzhiyun parent's address space 80*4882a593Smuzhiyun - clocks: Clock IDs array as required by the controller. 81*4882a593Smuzhiyun - clock-names: Names of clocks corresponding to IDs in the clock property. 82*4882a593Smuzhiyun Following clock names shall be provided for different 83*4882a593Smuzhiyun compatibles: 84*4882a593Smuzhiyun - samsung,exynos5250-dwusb3: "usbdrd30", 85*4882a593Smuzhiyun - samsung,exynos5433-dwusb3: "aclk", "susp_clk", "pipe_pclk", 86*4882a593Smuzhiyun "phyclk", 87*4882a593Smuzhiyun - samsung,exynos7-dwusb3: "usbdrd30", "usbdrd30_susp_clk", 88*4882a593Smuzhiyun "usbdrd30_axius_clk" 89*4882a593Smuzhiyun - vdd10-supply: 1.0V powr supply 90*4882a593Smuzhiyun - vdd33-supply: 3.0V/3.3V power supply 91*4882a593Smuzhiyun 92*4882a593SmuzhiyunSub-nodes: 93*4882a593SmuzhiyunThe dwc3 core should be added as subnode to Exynos dwc3 glue. 94*4882a593Smuzhiyun- dwc3 : 95*4882a593Smuzhiyun The binding details of dwc3 can be found in: 96*4882a593Smuzhiyun Documentation/devicetree/bindings/usb/dwc3.txt 97*4882a593Smuzhiyun 98*4882a593SmuzhiyunExample: 99*4882a593Smuzhiyun usb@12000000 { 100*4882a593Smuzhiyun compatible = "samsung,exynos5250-dwusb3"; 101*4882a593Smuzhiyun clocks = <&clock 286>; 102*4882a593Smuzhiyun clock-names = "usbdrd30"; 103*4882a593Smuzhiyun #address-cells = <1>; 104*4882a593Smuzhiyun #size-cells = <1>; 105*4882a593Smuzhiyun ranges; 106*4882a593Smuzhiyun vdd10-supply = <&ldo11_reg>; 107*4882a593Smuzhiyun vdd33-supply = <&ldo9_reg>; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun dwc3 { 110*4882a593Smuzhiyun compatible = "synopsys,dwc3"; 111*4882a593Smuzhiyun reg = <0x12000000 0x10000>; 112*4882a593Smuzhiyun interrupts = <0 72 0>; 113*4882a593Smuzhiyun usb-phy = <&usb2_phy &usb3_phy>; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun }; 116