1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Generic DWC3 Glue layer
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 - 2018 Xilinx, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based on dwc3-omap.c.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm-generic/io.h>
12*4882a593Smuzhiyun #include <dm.h>
13*4882a593Smuzhiyun #include <dm/device-internal.h>
14*4882a593Smuzhiyun #include <dm/lists.h>
15*4882a593Smuzhiyun #include <dwc3-uboot.h>
16*4882a593Smuzhiyun #include <linux/usb/ch9.h>
17*4882a593Smuzhiyun #include <linux/usb/gadget.h>
18*4882a593Smuzhiyun #include <malloc.h>
19*4882a593Smuzhiyun #include <usb.h>
20*4882a593Smuzhiyun #include "core.h"
21*4882a593Smuzhiyun #include "gadget.h"
22*4882a593Smuzhiyun #include <reset.h>
23*4882a593Smuzhiyun #include <clk.h>
24*4882a593Smuzhiyun #include <usb/xhci.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun struct dwc3_glue_data {
27*4882a593Smuzhiyun struct clk_bulk clks;
28*4882a593Smuzhiyun struct reset_ctl_bulk resets;
29*4882a593Smuzhiyun fdt_addr_t regs;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun struct dwc3_generic_plat {
33*4882a593Smuzhiyun fdt_addr_t base;
34*4882a593Smuzhiyun u32 maximum_speed;
35*4882a593Smuzhiyun enum usb_dr_mode dr_mode;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun struct dwc3_generic_priv {
39*4882a593Smuzhiyun void *base;
40*4882a593Smuzhiyun struct dwc3 dwc3;
41*4882a593Smuzhiyun struct phy *phys;
42*4882a593Smuzhiyun int num_phys;
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun struct dwc3_generic_host_priv {
46*4882a593Smuzhiyun struct xhci_ctrl xhci_ctrl;
47*4882a593Smuzhiyun struct dwc3_generic_priv gen_priv;
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
dwc3_generic_probe(struct udevice * dev,struct dwc3_generic_priv * priv)50*4882a593Smuzhiyun static int dwc3_generic_probe(struct udevice *dev,
51*4882a593Smuzhiyun struct dwc3_generic_priv *priv)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun int rc;
54*4882a593Smuzhiyun struct dwc3_generic_plat *plat = dev_get_platdata(dev);
55*4882a593Smuzhiyun struct dwc3 *dwc3 = &priv->dwc3;
56*4882a593Smuzhiyun struct dwc3_glue_data *glue = dev_get_platdata(dev->parent);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun dwc3->dev = dev;
59*4882a593Smuzhiyun dwc3->maximum_speed = plat->maximum_speed;
60*4882a593Smuzhiyun dwc3->dr_mode = plat->dr_mode;
61*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(OF_CONTROL)
62*4882a593Smuzhiyun dwc3_of_parse(dwc3);
63*4882a593Smuzhiyun #endif
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /*
66*4882a593Smuzhiyun * It must hold whole USB3.0 OTG controller in resetting to hold pipe
67*4882a593Smuzhiyun * power state in P2 before initializing TypeC PHY on RK3399 platform.
68*4882a593Smuzhiyun */
69*4882a593Smuzhiyun if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
70*4882a593Smuzhiyun reset_assert_bulk(&glue->resets);
71*4882a593Smuzhiyun udelay(1);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun rc = dwc3_setup_phy(dev, &priv->phys, &priv->num_phys);
75*4882a593Smuzhiyun if (rc)
76*4882a593Smuzhiyun return rc;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
79*4882a593Smuzhiyun reset_deassert_bulk(&glue->resets);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
82*4882a593Smuzhiyun dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun rc = dwc3_init(dwc3);
86*4882a593Smuzhiyun if (rc) {
87*4882a593Smuzhiyun unmap_physmem(priv->base, MAP_NOCACHE);
88*4882a593Smuzhiyun return rc;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
dwc3_generic_remove(struct udevice * dev,struct dwc3_generic_priv * priv)94*4882a593Smuzhiyun static int dwc3_generic_remove(struct udevice *dev,
95*4882a593Smuzhiyun struct dwc3_generic_priv *priv)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun struct dwc3 *dwc3 = &priv->dwc3;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun dwc3_remove(dwc3);
100*4882a593Smuzhiyun dwc3_shutdown_phy(dev, priv->phys, priv->num_phys);
101*4882a593Smuzhiyun unmap_physmem(dwc3->regs, MAP_NOCACHE);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun return 0;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
dwc3_generic_ofdata_to_platdata(struct udevice * dev)106*4882a593Smuzhiyun static int dwc3_generic_ofdata_to_platdata(struct udevice *dev)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun struct dwc3_generic_plat *plat = dev_get_platdata(dev);
109*4882a593Smuzhiyun ofnode node = dev->node;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun plat->base = dev_read_addr(dev);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun plat->maximum_speed = usb_get_maximum_speed(node);
114*4882a593Smuzhiyun if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
115*4882a593Smuzhiyun pr_info("No USB maximum speed specified. Using super speed\n");
116*4882a593Smuzhiyun plat->maximum_speed = USB_SPEED_SUPER;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun plat->dr_mode = usb_get_dr_mode(node);
120*4882a593Smuzhiyun if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
121*4882a593Smuzhiyun pr_err("Invalid usb mode setup\n");
122*4882a593Smuzhiyun return -ENODEV;
123*4882a593Smuzhiyun } else if (plat->dr_mode != USB_DR_MODE_HOST &&
124*4882a593Smuzhiyun !strcmp(dev->driver->name, "dwc3-generic-host")) {
125*4882a593Smuzhiyun pr_info("Set dr_mode to HOST\n");
126*4882a593Smuzhiyun plat->dr_mode = USB_DR_MODE_HOST;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun return 0;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(DM_USB_GADGET)
dm_usb_gadget_handle_interrupts(struct udevice * dev)133*4882a593Smuzhiyun int dm_usb_gadget_handle_interrupts(struct udevice *dev)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun struct dwc3_generic_priv *priv = dev_get_priv(dev);
136*4882a593Smuzhiyun struct dwc3 *dwc3 = &priv->dwc3;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun dwc3_gadget_uboot_handle_interrupt(dwc3);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
dwc3_generic_peripheral_probe(struct udevice * dev)143*4882a593Smuzhiyun static int dwc3_generic_peripheral_probe(struct udevice *dev)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun struct dwc3_generic_priv *priv = dev_get_priv(dev);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun return dwc3_generic_probe(dev, priv);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
dwc3_generic_peripheral_remove(struct udevice * dev)150*4882a593Smuzhiyun static int dwc3_generic_peripheral_remove(struct udevice *dev)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun struct dwc3_generic_priv *priv = dev_get_priv(dev);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return dwc3_generic_remove(dev, priv);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun U_BOOT_DRIVER(dwc3_generic_peripheral) = {
158*4882a593Smuzhiyun .name = "dwc3-generic-peripheral",
159*4882a593Smuzhiyun .id = UCLASS_USB_GADGET_GENERIC,
160*4882a593Smuzhiyun .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
161*4882a593Smuzhiyun .probe = dwc3_generic_peripheral_probe,
162*4882a593Smuzhiyun .remove = dwc3_generic_peripheral_remove,
163*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct dwc3_generic_priv),
164*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun #endif
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
dwc3_generic_host_probe(struct udevice * dev)169*4882a593Smuzhiyun static int dwc3_generic_host_probe(struct udevice *dev)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun struct xhci_hcor *hcor;
172*4882a593Smuzhiyun struct xhci_hccr *hccr;
173*4882a593Smuzhiyun struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
174*4882a593Smuzhiyun int rc;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun rc = dwc3_generic_probe(dev, &priv->gen_priv);
177*4882a593Smuzhiyun if (rc)
178*4882a593Smuzhiyun return rc;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun hccr = (struct xhci_hccr *)priv->gen_priv.base;
181*4882a593Smuzhiyun hcor = (struct xhci_hcor *)(priv->gen_priv.base +
182*4882a593Smuzhiyun HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return xhci_register(dev, hccr, hcor);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
dwc3_generic_host_remove(struct udevice * dev)187*4882a593Smuzhiyun static int dwc3_generic_host_remove(struct udevice *dev)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
190*4882a593Smuzhiyun int rc;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun rc = xhci_deregister(dev);
193*4882a593Smuzhiyun if (rc)
194*4882a593Smuzhiyun return rc;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun return dwc3_generic_remove(dev, &priv->gen_priv);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun U_BOOT_DRIVER(dwc3_generic_host) = {
200*4882a593Smuzhiyun .name = "dwc3-generic-host",
201*4882a593Smuzhiyun .id = UCLASS_USB,
202*4882a593Smuzhiyun .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
203*4882a593Smuzhiyun .probe = dwc3_generic_host_probe,
204*4882a593Smuzhiyun .remove = dwc3_generic_host_remove,
205*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct dwc3_generic_host_priv),
206*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
207*4882a593Smuzhiyun .ops = &xhci_usb_ops,
208*4882a593Smuzhiyun .flags = DM_FLAG_ALLOC_PRIV_DMA,
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun #endif
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun struct dwc3_glue_ops {
213*4882a593Smuzhiyun void (*select_dr_mode)(struct udevice *dev, int index,
214*4882a593Smuzhiyun enum usb_dr_mode mode);
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
dwc3_ti_select_dr_mode(struct udevice * dev,int index,enum usb_dr_mode mode)217*4882a593Smuzhiyun void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
218*4882a593Smuzhiyun enum usb_dr_mode mode)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun #define USBOTGSS_UTMI_OTG_STATUS 0x0084
221*4882a593Smuzhiyun #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* UTMI_OTG_STATUS REGISTER */
224*4882a593Smuzhiyun #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE BIT(31)
225*4882a593Smuzhiyun #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT BIT(9)
226*4882a593Smuzhiyun #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
227*4882a593Smuzhiyun #define USBOTGSS_UTMI_OTG_STATUS_IDDIG BIT(4)
228*4882a593Smuzhiyun #define USBOTGSS_UTMI_OTG_STATUS_SESSEND BIT(3)
229*4882a593Smuzhiyun #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID BIT(2)
230*4882a593Smuzhiyun #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID BIT(1)
231*4882a593Smuzhiyun enum dwc3_omap_utmi_mode {
232*4882a593Smuzhiyun DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
233*4882a593Smuzhiyun DWC3_OMAP_UTMI_MODE_HW,
234*4882a593Smuzhiyun DWC3_OMAP_UTMI_MODE_SW,
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun u32 use_id_pin;
238*4882a593Smuzhiyun u32 host_mode;
239*4882a593Smuzhiyun u32 reg;
240*4882a593Smuzhiyun u32 utmi_mode;
241*4882a593Smuzhiyun u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun struct dwc3_glue_data *glue = dev_get_platdata(dev);
244*4882a593Smuzhiyun void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun if (device_is_compatible(dev, "ti,am437x-dwc3"))
247*4882a593Smuzhiyun utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun utmi_mode = dev_read_u32_default(dev, "utmi-mode",
250*4882a593Smuzhiyun DWC3_OMAP_UTMI_MODE_UNKNOWN);
251*4882a593Smuzhiyun if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
252*4882a593Smuzhiyun debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
253*4882a593Smuzhiyun dev->name);
254*4882a593Smuzhiyun mode = USB_DR_MODE_PERIPHERAL;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun switch (mode) {
258*4882a593Smuzhiyun case USB_DR_MODE_PERIPHERAL:
259*4882a593Smuzhiyun use_id_pin = 0;
260*4882a593Smuzhiyun host_mode = 0;
261*4882a593Smuzhiyun break;
262*4882a593Smuzhiyun case USB_DR_MODE_HOST:
263*4882a593Smuzhiyun use_id_pin = 0;
264*4882a593Smuzhiyun host_mode = 1;
265*4882a593Smuzhiyun break;
266*4882a593Smuzhiyun case USB_DR_MODE_OTG:
267*4882a593Smuzhiyun default:
268*4882a593Smuzhiyun use_id_pin = 1;
269*4882a593Smuzhiyun host_mode = 0;
270*4882a593Smuzhiyun break;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun reg = readl(base + utmi_status_offset);
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
276*4882a593Smuzhiyun if (!use_id_pin)
277*4882a593Smuzhiyun reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun writel(reg, base + utmi_status_offset);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND |
282*4882a593Smuzhiyun USBOTGSS_UTMI_OTG_STATUS_VBUSVALID |
283*4882a593Smuzhiyun USBOTGSS_UTMI_OTG_STATUS_IDDIG);
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID |
286*4882a593Smuzhiyun USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun if (!host_mode)
289*4882a593Smuzhiyun reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG |
290*4882a593Smuzhiyun USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun writel(reg, base + utmi_status_offset);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun unmap_physmem(base, MAP_NOCACHE);
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun struct dwc3_glue_ops ti_ops = {
298*4882a593Smuzhiyun .select_dr_mode = dwc3_ti_select_dr_mode,
299*4882a593Smuzhiyun };
300*4882a593Smuzhiyun
dwc3_glue_bind(struct udevice * parent)301*4882a593Smuzhiyun static int dwc3_glue_bind(struct udevice *parent)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun ofnode node;
304*4882a593Smuzhiyun int ret;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun ofnode_for_each_subnode(node, parent->node) {
307*4882a593Smuzhiyun const char *name = ofnode_get_name(node);
308*4882a593Smuzhiyun enum usb_dr_mode dr_mode;
309*4882a593Smuzhiyun struct udevice *dev;
310*4882a593Smuzhiyun const char *driver = NULL;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun debug("%s: subnode name: %s\n", __func__, name);
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun dr_mode = usb_get_dr_mode(node);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun switch (dr_mode) {
317*4882a593Smuzhiyun case USB_DR_MODE_OTG:
318*4882a593Smuzhiyun #if defined(CONFIG_ARCH_ROCKCHIP) && defined(CONFIG_USB_XHCI_HCD)
319*4882a593Smuzhiyun debug("%s: dr_mode: force to HOST\n", __func__);
320*4882a593Smuzhiyun driver = "dwc3-generic-host";
321*4882a593Smuzhiyun break;
322*4882a593Smuzhiyun #endif
323*4882a593Smuzhiyun case USB_DR_MODE_PERIPHERAL:
324*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(DM_USB_GADGET)
325*4882a593Smuzhiyun debug("%s: dr_mode: OTG or Peripheral\n", __func__);
326*4882a593Smuzhiyun driver = "dwc3-generic-peripheral";
327*4882a593Smuzhiyun #endif
328*4882a593Smuzhiyun break;
329*4882a593Smuzhiyun #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
330*4882a593Smuzhiyun case USB_DR_MODE_HOST:
331*4882a593Smuzhiyun debug("%s: dr_mode: HOST\n", __func__);
332*4882a593Smuzhiyun driver = "dwc3-generic-host";
333*4882a593Smuzhiyun break;
334*4882a593Smuzhiyun #endif
335*4882a593Smuzhiyun default:
336*4882a593Smuzhiyun debug("%s: unsupported dr_mode\n", __func__);
337*4882a593Smuzhiyun return -ENODEV;
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun if (!driver)
341*4882a593Smuzhiyun continue;
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun ret = device_bind_driver_to_node(parent, driver, name,
344*4882a593Smuzhiyun node, &dev);
345*4882a593Smuzhiyun if (ret) {
346*4882a593Smuzhiyun debug("%s: not able to bind usb device mode\n",
347*4882a593Smuzhiyun __func__);
348*4882a593Smuzhiyun return ret;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun return 0;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun
dwc3_glue_reset_init(struct udevice * dev,struct dwc3_glue_data * glue)355*4882a593Smuzhiyun static int dwc3_glue_reset_init(struct udevice *dev,
356*4882a593Smuzhiyun struct dwc3_glue_data *glue)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun int ret;
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun ret = reset_get_bulk(dev, &glue->resets);
361*4882a593Smuzhiyun if (ret == -ENOTSUPP || ret == -ENOENT)
362*4882a593Smuzhiyun return 0;
363*4882a593Smuzhiyun else if (ret)
364*4882a593Smuzhiyun return ret;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun ret = reset_deassert_bulk(&glue->resets);
367*4882a593Smuzhiyun if (ret) {
368*4882a593Smuzhiyun reset_release_bulk(&glue->resets);
369*4882a593Smuzhiyun return ret;
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun return 0;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun
dwc3_glue_clk_init(struct udevice * dev,struct dwc3_glue_data * glue)375*4882a593Smuzhiyun static int dwc3_glue_clk_init(struct udevice *dev,
376*4882a593Smuzhiyun struct dwc3_glue_data *glue)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun int ret;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun ret = clk_get_bulk(dev, &glue->clks);
381*4882a593Smuzhiyun if (ret == -ENOSYS || ret == -ENOENT)
382*4882a593Smuzhiyun return 0;
383*4882a593Smuzhiyun if (ret)
384*4882a593Smuzhiyun return ret;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(CLK)
387*4882a593Smuzhiyun ret = clk_enable_bulk(&glue->clks);
388*4882a593Smuzhiyun if (ret) {
389*4882a593Smuzhiyun clk_release_bulk(&glue->clks);
390*4882a593Smuzhiyun return ret;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun #endif
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun return 0;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
dwc3_glue_probe(struct udevice * dev)397*4882a593Smuzhiyun static int dwc3_glue_probe(struct udevice *dev)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev);
400*4882a593Smuzhiyun struct dwc3_glue_data *glue = dev_get_platdata(dev);
401*4882a593Smuzhiyun struct udevice *child = NULL;
402*4882a593Smuzhiyun int index = 0;
403*4882a593Smuzhiyun int ret;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun glue->regs = dev_read_addr(dev);
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun ret = dwc3_glue_clk_init(dev, glue);
408*4882a593Smuzhiyun if (ret)
409*4882a593Smuzhiyun return ret;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun ret = dwc3_glue_reset_init(dev, glue);
412*4882a593Smuzhiyun if (ret)
413*4882a593Smuzhiyun return ret;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun ret = device_find_first_child(dev, &child);
416*4882a593Smuzhiyun if (ret)
417*4882a593Smuzhiyun return ret;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun if (glue->resets.count < 1) {
420*4882a593Smuzhiyun ret = dwc3_glue_reset_init(child, glue);
421*4882a593Smuzhiyun if (ret)
422*4882a593Smuzhiyun return ret;
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun while (child) {
426*4882a593Smuzhiyun enum usb_dr_mode dr_mode;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun dr_mode = usb_get_dr_mode(child->node);
429*4882a593Smuzhiyun device_find_next_child(&child);
430*4882a593Smuzhiyun if (ops && ops->select_dr_mode)
431*4882a593Smuzhiyun ops->select_dr_mode(dev, index, dr_mode);
432*4882a593Smuzhiyun index++;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun return 0;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun
dwc3_glue_remove(struct udevice * dev)438*4882a593Smuzhiyun static int dwc3_glue_remove(struct udevice *dev)
439*4882a593Smuzhiyun {
440*4882a593Smuzhiyun struct dwc3_glue_data *glue = dev_get_platdata(dev);
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun reset_release_bulk(&glue->resets);
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun clk_release_bulk(&glue->clks);
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun return 0;
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun static const struct udevice_id dwc3_glue_ids[] = {
450*4882a593Smuzhiyun { .compatible = "xlnx,zynqmp-dwc3" },
451*4882a593Smuzhiyun { .compatible = "ti,keystone-dwc3"},
452*4882a593Smuzhiyun { .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
453*4882a593Smuzhiyun { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
454*4882a593Smuzhiyun { .compatible = "rockchip,rk3328-dwc3" },
455*4882a593Smuzhiyun { .compatible = "rockchip,rk3399-dwc3" },
456*4882a593Smuzhiyun { }
457*4882a593Smuzhiyun };
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun U_BOOT_DRIVER(dwc3_generic_wrapper) = {
460*4882a593Smuzhiyun .name = "dwc3-generic-wrapper",
461*4882a593Smuzhiyun .id = UCLASS_NOP,
462*4882a593Smuzhiyun .of_match = dwc3_glue_ids,
463*4882a593Smuzhiyun .bind = dwc3_glue_bind,
464*4882a593Smuzhiyun .probe = dwc3_glue_probe,
465*4882a593Smuzhiyun .remove = dwc3_glue_remove,
466*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct dwc3_glue_data),
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun };
469