| /OK3568_Linux_fs/kernel/arch/arm/mach-ep93xx/ |
| H A D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-ep93xx/dma.c
9 * This work is based on the original dma-m2p implementation with
18 #include <linux/dma-mapping.h>
24 #include <linux/platform_data/dma-ep93xx.h>
33 * DMA M2P channels.
36 * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
38 * I2S contains 3 Tx and 3 Rx DMA Channels
39 * AAC contains 3 Tx and 3 Rx DMA Channels
40 * UART1 contains 1 Tx and 1 Rx DMA Channels
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/ |
| H A D | brcm,bcm2835-dma.txt | 1 * BCM2835 DMA controller
3 The BCM2835 DMA controller has 16 channels in total.
4 Only the lower 13 channels have an associated IRQ.
5 Some arbitrary channels are used by the firmware
7 The channels 0,2 and 3 have special functionality
11 - compatible: Should be "brcm,bcm2835-dma".
12 - reg: Should contain DMA registers location and length.
13 - interrupts: Should contain the DMA interrupts associated
14 to the DMA channels in ascending order.
15 - interrupt-names: Should contain the names of the interrupt
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| H A D | ste-dma40.txt | 1 * DMA40 DMA Controller
4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
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| H A D | ingenic,dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/ingenic,dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs DMA Controller DT bindings
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: "dma-controller.yaml#"
18 - ingenic,jz4740-dma
19 - ingenic,jz4725b-dma
20 - ingenic,jz4770-dma
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| H A D | mmp-dma.txt | 1 * MARVELL MMP DMA controller
3 Marvell Peripheral DMA Controller
7 - compatible: Should be "marvell,pdma-1.0"
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
13 - #dma-channels: Number of DMA channels supported by the controller (defaults
15 - #dma-requests: Number of DMA requestor lines supported by the controller
18 "marvell,pdma-1.0"
26 * while DMA controller may not able to distinguish the irq channel
27 * Using this method, interrupt-parent is required as demuxer
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| H A D | ti-edma.txt | 4 Controller(s) (TC). The CC is the main entry for DMA users since it is
5 responsible for the DMA channel handling, while the TCs are responsible to
6 execute the actual DMA tansfer.
8 ------------------------------------------------------------------------------
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
20 - reg: Memory map of eDMA CC
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| H A D | owl-dma.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
15 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 - $ref: "dma-controller.yaml#"
23 - actions,s900-dma
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| H A D | snps,dw-axi-dmac.txt | 1 Synopsys DesignWare AXI DMA Controller
4 - compatible: "snps,axi-dma-1.01a"
5 - reg: Address range of the DMAC registers. This should include
6 all of the per-channel registers.
7 - interrupt: Should contain the DMAC interrupt number.
8 - dma-channels: Number of channels supported by hardware.
9 - snps,dma-masters: Number of AXI masters supported by the hardware.
10 - snps,data-width: Maximum AXI data width supported by hardware.
11 (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
12 - snps,priority: Priority of channel. Array size is equal to the number of
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| H A D | dma-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/dma-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DMA Engine Generic Binding
10 - Vinod Koul <vkoul@kernel.org>
13 Generic binding to provide a way for a driver using DMA Engine to
14 retrieve the DMA request or channel information that goes from a
15 hardware device to a DMA controller.
20 "#dma-cells":
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| H A D | snps,dma-spear1340.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: "dma-controller.yaml#"
18 const: snps,dma-spear1340
20 "#dma-cells":
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| H A D | fsl-mxs-dma.txt | 1 * Freescale MXS DMA
4 - compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx"
5 - reg : Should contain registers location and length
6 - interrupts : Should contain the interrupt numbers of DMA channels.
8 - #dma-cells : Must be <1>. The number cell specifies the channel ID.
9 - dma-channels : Number of channels supported by the DMA controller
12 - interrupt-names : Name of DMA channel interrupts
19 dma_apbh: dma-apbh@80004000 {
20 compatible = "fsl,imx28-dma-apbh";
26 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
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| H A D | fsl-edma.txt | 3 The eDMA channels have multiplex capability by programmble memory-mapped
4 registers. channels are split into two groups, called DMAMUX0 and DMAMUX1,
5 specific DMA request source can only be multiplexed by any channel of certain
10 - compatible :
11 - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
12 - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp
13 - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the
15 - reg : Specifies base physical address(s) and size of the eDMA registers.
19 - interrupts : A list of interrupt-specifiers, one for each entry in
20 interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel
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| H A D | st_fdma.txt | 3 The FDMA is a general-purpose direct memory access controller capable of
4 supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
10 - compatible : Should be one of
11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14 - reg : Should contain an entry for each name in reg-names
15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
16 - interrupts : Should contain one interrupt shared by all channels
17 - dma-channels : Number of channels supported by the controller
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| H A D | fsl-qdma.txt | 4 This device follows the generic DMA bindings defined in dma/dma.txt.
8 - compatible: Must be one of
9 "fsl,ls1021a-qdma": for LS1021A Board
10 "fsl,ls1028a-qdma": for LS1028A Board
11 "fsl,ls1043a-qdma": for ls1043A Board
12 "fsl,ls1046a-qdma": for ls1046A Board
13 - reg: Should contain the register's base address and length.
14 - interrupts: Should contain a reference to the interrupt used by this
16 - interrupt-names: Should contain interrupt names:
17 "qdma-queue0": the block0 interrupt
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| H A D | qcom_hidma_mgmt.txt | 3 Qualcomm Technologies HIDMA is a high speed DMA device. It only supports
7 Each HIDMA HW instance consists of multiple DMA channels. These channels
9 among channels based on the priority and weight assignments.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
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| H A D | zxdma.txt | 1 * ZTE ZX296702 DMA controller
4 - compatible: Should be "zte,zx296702-dma"
5 - reg: Should contain DMA registers location and length.
6 - interrupts: Should contain one interrupt shared by all channel
7 - #dma-cells: see dma.txt, should be 1, para number
8 - dma-channels: physical channels supported
9 - dma-requests: virtual channels supported, each virtual channel
11 - clocks: clock required
16 dma: dma-controller@09c00000{
17 compatible = "zte,zx296702-dma";
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| /OK3568_Linux_fs/kernel/drivers/iio/adc/ |
| H A D | ti_am335x_adc.c | 4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
34 #include <linux/dma-mapping.h>
51 struct tiadc_dma dma; member
53 int channels; member
64 return readl(adc->mfd_tscadc->tscadc_base + reg); in tiadc_readl()
70 writel(val, adc->mfd_tscadc->tscadc_base + reg); in tiadc_writel()
77 step_en = ((1 << adc_dev->channels) - 1); in get_adc_step_mask()
78 step_en <<= TOTAL_STEPS - adc_dev->channels + 1; in get_adc_step_mask()
87 for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) { in get_adc_chan_step_mask()
88 if (chan->channel == adc_dev->channel_line[i]) { in get_adc_chan_step_mask()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/xilinx/ |
| H A D | xilinx_dma.txt | 2 It can be configured to have one channel or two channels. If configured
3 as two channels, one is to transmit to the video device and another is
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
7 target devices. It can be configured to have one channel or two channels.
8 If configured as two channels, one is to transmit to the device and another
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
16 and receive channels.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
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| /OK3568_Linux_fs/kernel/arch/mips/include/asm/ |
| H A D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
5 * High DMA channel support & info by Hannu Savolainen
9 * and can only be used for expansion cards. Onboard DMA controllers, such
30 * NOTES about DMA transfers:
32 * controller 1: channels 0-3, byte operations, ports 00-1F
33 * controller 2: channels 4-7, word operations, ports C0-DF
35 * - ALL registers are 8 bits only, regardless of transfer size
36 * - channel 4 is not used - cascades 1 into 2.
37 * - channels 0-3 are byte - addresses/counts are for physical bytes
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| /OK3568_Linux_fs/kernel/arch/x86/include/asm/ |
| H A D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
5 * High DMA channel support & info by Hannu Savolainen
24 * NOTES about DMA transfers:
26 * controller 1: channels 0-3, byte operations, ports 00-1F
27 * controller 2: channels 4-7, word operations, ports C0-DF
29 * - ALL registers are 8 bits only, regardless of transfer size
30 * - channel 4 is not used - cascades 1 into 2.
31 * - channels 0-3 are byte - addresses/counts are for physical bytes
32 * - channels 5-7 are word - addresses/counts are for physical words
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| /OK3568_Linux_fs/kernel/include/linux/platform_data/ |
| H A D | dma-ep93xx.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/dma-mapping.h>
10 * M2P channels.
25 /* M2M channels */
30 * struct ep93xx_dma_data - configuration data for the EP93xx dmaengine
36 * function. Note that this is only needed for slave/cyclic channels. For
37 * memcpy channels %NULL data should be passed.
46 * struct ep93xx_dma_chan_data - platform specific data for a DMA channel
58 * struct ep93xx_dma_platform_data - platform data for the dmaengine driver
59 * @channels: array of channels which are passed to the driver
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| /OK3568_Linux_fs/kernel/arch/alpha/include/asm/ |
| H A D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * include/asm-alpha/dma.h
5 * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
6 * use ISA-compatible dma. The only extension is support for high-page
7 * registers that allow to set the top 8 bits of a 32-bit DMA address.
8 * This register should be written last when setting up a DMA address
9 * as this will also enable DMA across 64 KB boundaries.
12 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
13 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
15 * High DMA channel support & info by Hannu Savolainen
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| /OK3568_Linux_fs/kernel/arch/powerpc/include/asm/ |
| H A D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Defines for using and allocating dma channels.
9 * High DMA channel support & info by Hannu Savolainen
19 * basically just enough here to get kernel/dma.c to compile.
29 /* The maximum address that we can perform a DMA transfer to on this platform */
42 * NOTES about DMA transfers:
44 * controller 1: channels 0-3, byte operations, ports 00-1F
45 * controller 2: channels 4-7, word operations, ports C0-DF
47 * - ALL registers are 8 bits only, regardless of transfer size
48 * - channel 4 is not used - cascades 1 into 2.
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| /OK3568_Linux_fs/kernel/arch/sh/drivers/dma/ |
| H A D | dma-api.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/drivers/dma/dma-api.c
5 * SuperH-specific DMA management API
19 #include <asm/dma.h>
33 if ((chan < info->first_vchannel_nr) || in get_dma_info()
34 (chan >= info->first_vchannel_nr + info->nr_channels)) in get_dma_info()
49 if (dmac_name && (strcmp(dmac_name, info->name) != 0)) in get_dma_info_by_name()
68 nr += info->nr_channels; in get_nr_channels()
80 return ERR_PTR(-EINVAL); in get_dma_channel()
82 for (i = 0; i < info->nr_channels; i++) { in get_dma_channel()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/ti/ |
| H A D | k3-udma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments K3 NAVSS Unified DMA Device Tree Bindings
10 - Peter Ujfalusi <peter.ujfalusi@ti.com>
13 The UDMA-P is intended to perform similar (but significantly upgraded)
14 functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
16 The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
19 Multiple Tx and Rx channels are provided within the DMA which allow multiple
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