1*4882a593Smuzhiyun* MARVELL MMP DMA controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunMarvell Peripheral DMA Controller 4*4882a593SmuzhiyunUsed platforms: pxa688, pxa910, pxa3xx, etc 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: Should be "marvell,pdma-1.0" 8*4882a593Smuzhiyun- reg: Should contain DMA registers location and length. 9*4882a593Smuzhiyun- interrupts: Either contain all of the per-channel DMA interrupts 10*4882a593Smuzhiyun or one irq for pdma device 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunOptional properties: 13*4882a593Smuzhiyun- #dma-channels: Number of DMA channels supported by the controller (defaults 14*4882a593Smuzhiyun to 32 when not specified) 15*4882a593Smuzhiyun- #dma-requests: Number of DMA requestor lines supported by the controller 16*4882a593Smuzhiyun (defaults to 32 when not specified) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun"marvell,pdma-1.0" 19*4882a593SmuzhiyunUsed platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExamples: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun/* 24*4882a593Smuzhiyun * Each channel has specific irq 25*4882a593Smuzhiyun * ICU parse out irq channel from ICU register, 26*4882a593Smuzhiyun * while DMA controller may not able to distinguish the irq channel 27*4882a593Smuzhiyun * Using this method, interrupt-parent is required as demuxer 28*4882a593Smuzhiyun * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq, 29*4882a593Smuzhiyun * 18~21 is ADMA irq 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyunpdma: dma-controller@d4000000 { 32*4882a593Smuzhiyun compatible = "marvell,pdma-1.0"; 33*4882a593Smuzhiyun reg = <0xd4000000 0x10000>; 34*4882a593Smuzhiyun interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; 35*4882a593Smuzhiyun interrupt-parent = <&intcmux32>; 36*4882a593Smuzhiyun #dma-channels = <16>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun/* 40*4882a593Smuzhiyun * One irq for all channels 41*4882a593Smuzhiyun * Dmaengine driver (DMA controller) distinguish irq channel via 42*4882a593Smuzhiyun * parsing internal register 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyunpdma: dma-controller@d4000000 { 45*4882a593Smuzhiyun compatible = "marvell,pdma-1.0"; 46*4882a593Smuzhiyun reg = <0xd4000000 0x10000>; 47*4882a593Smuzhiyun interrupts = <47>; 48*4882a593Smuzhiyun #dma-channels = <16>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunMarvell Two Channel DMA Controller used specifically for audio 53*4882a593SmuzhiyunUsed platforms: pxa688, pxa910 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunRequired properties: 56*4882a593Smuzhiyun- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ" 57*4882a593Smuzhiyun- reg: Should contain DMA registers location and length. 58*4882a593Smuzhiyun- interrupts: Either contain all of the per-channel DMA interrupts 59*4882a593Smuzhiyun or one irq for dma device 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun"marvell,adma-1.0" used on pxa688 62*4882a593Smuzhiyun"marvell,pxa910-squ" used on pxa910 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunExamples: 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun/* each channel has specific irq */ 67*4882a593Smuzhiyunadma0: dma-controller@d42a0800 { 68*4882a593Smuzhiyun compatible = "marvell,adma-1.0"; 69*4882a593Smuzhiyun reg = <0xd42a0800 0x100>; 70*4882a593Smuzhiyun interrupts = <18 19>; 71*4882a593Smuzhiyun interrupt-parent = <&intcmux32>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun/* One irq for all channels */ 75*4882a593Smuzhiyunsqu: dma-controller@d42a0800 { 76*4882a593Smuzhiyun compatible = "marvell,pxa910-squ"; 77*4882a593Smuzhiyun reg = <0xd42a0800 0x100>; 78*4882a593Smuzhiyun interrupts = <46>; 79*4882a593Smuzhiyun }; 80